Wireless communications systems and methods for multiple operating system multiple user detection

ABSTRACT

The invention provides methods and apparatus for multiple user detection (MUD) processing that have application, for example, in improving the capacity CDMA and other wireless base stations. One aspect of the invention provides a multiprocessor, multiuser detection system for detecting user transmitted symbols in CDMA short-code spectrum waveforms. A first processing element generates a matrix (hereinafter, “gamma matrix”) that represents a correlation between a short-code associated with one user and those associated with one or more other users. A set of second processing elements generates, e.g., from the gamma matrix, a matrix (hereinafter, “R-matrix”) that represents cross-correlations among user waveforms based on their amplitudes and time lags. A third procesing element produces estimates of the user transmitted symbols as a function of the R-matrix.

[0001] This application claims the benefit of priority of (i) U.S.Provisional Application Serial No. 60/275,846 filed Mar. 14, 2001,entitled “Improved Wireless Communications Systems and Methods”; (ii)U.S. Provisional Application Serial No. 60/289,600 filed May 7, 2001,entitled “Improved Wireless Communications Systems and Methods UsingLong-Code Multi-User Detection'” and (iii) U.S. Provisional ApplicationSerial No. 60/295,060 filed Jun. 1, 2001 entitled “Improved WirelessCommunications Systems and Methods for a Communications Computer,” theteachings all of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The invention pertains to wireless communications and, moreparticularly, by way of example, to methods and apparatus providingmultiple user detection for use in code division multiple access (CDMA)communications. The invention has application, by way of non-limitingexample, in improving the capacity of cellular phone base stations.

[0003] Code-division multiple access (CDMA) is used increasingly inwireless communications. It is a form of multiplexing communications,e.g., between cellular phones and base stations, based on distinctdigital codes in the communication signals. This can be contrasted withother wireless protocols, such as frequency-division multiple access andtime-division multiple access, in which multiplexing is based on the useof orthogonal frequency bands and orthogonal time-slots, respectively.

[0004] A limiting factor in CDMA communication and, particularly, inso-called direct sequence CDMA (DS-CDMA), is interference—both thatwrought on individual transmissions by buildings and other“environmental” factors, as well that between multiple simultaneouscommunications, e.g., multiple cellular phone users in the samegeographic area using their phones at the same time. The latter isreferred to as multiple access interference (MAI). Along withenvironmental interference, it has effect of limiting the capacity ofcellular phone base stations, driving service quality below acceptablelevels when there are too many users.

[0005] A technique known as multi-user detection (MUD) is intended toreduce multiple access interference and, as a consequence, increasesbase station capacity. It can reduce interference not only betweenmultiple transmissions of like strength, but also that caused by usersso close to the base station as to otherwise overpower signals fromother users (the so-called near/far problem). MUD generally functions onthe principle that signals from multiple simultaneous users can bejointly used to improve detection of the signal from any single user.Many forms of MUD are discussed in the literature; surveys are providedin Moshavi, “Multi-User Detection for DS-CDMA Systems,” IEEECommunications Magazine (October, 1996) and Duel-Hallen et al,“Multiuser Detection for CDMA Systems,” IEEE Personal Communications(April 1995). Though a promising solution to increasing the capacity ofcellular phone base stations, MUD techniques are typically socomputationally intensive as to limit practical application.

[0006] An object of this invention is to provide improved methods andapparatus for wireless communications. A related object is to providesuch methods and apparatus for multi-user detection or interferencecancellation in code-division multiple access communications.

[0007] A further related object is to provide such methods and apparatusas provide improved short-code and/or long-code CDMA communications.

[0008] A further object of the invention is to provide such methods andapparatus as can be cost-effectively implemented and as require minimalchanges in existing wireless communications infrastructure.

[0009] A still further object of the invention is to provide methods andapparatus for executing multi-user detection and related algorithms inreal-time.

[0010] A still further object of the invention is to provide suchmethods and apparatus as manage faults for high-availability.

SUMMARY OF THE INVENTION

[0011] The foregoing and other objects are among those attained by theinvention which provides methods and apparatus for multiple userdetection (MUD) processing. These have application, for example, inimproving the capacity CDMA and other wireless base stations

[0012] Wireless Communications Systems and Methods for MultipleProcessor Based Multiple User Detection

[0013] One aspect of the invention provides a multiuser communicationsdevice for detecting user transmitted symbols in CDMA short-code spreadspectrum waveforms. A first processing element generates a matrix(hereinafter, “gamma matrix”) that represents a correlation between ashort-code associated with one user and those associated with one ormore other users. A set of second processing elements generates, e.g.,from the gamma matrix, a matrix (hereinafter, “R-matrix”) thatrepresents cross-correlations among user waveforms based on theiramplitudes and time lags. A third processing element produces estimatesof the user transmitted symbols as a function of the R-matrix.

[0014] In related aspects, the invention provides a multiusercommunications device in which a host controller performs a“partitioning function,” assigning to each second processing elementwithin the aforementioned set a portion of the R-matrix to generate.This partitioning can be a function of the number of users and thenumber of processing elements available in the set. According to relatedaspects of the invention, as users are added or removed from the spreadspectrum system, the host controller performs further partitioning,assigning each second processing element within the set a new portion ofthe R-matrix to generate.

[0015] Further related aspects of the invention provide a multiusercommunications device as described above in which the host controller iscoupled to the processing elements by way of a multi-port data switch.Still further related aspects of the invention provide such a device inwhich the first processing element transfers the gamma-matrix to the setof second processing elements via a memory element.

[0016] Similarly, the set of second processing elements place therespective portions of the R-matrix in memory accessible to the thirdprocessing element via the data switch. Further related aspects of theinvention provide devices as described above in which the hostcontroller effects data flow synchronization between the firstprocessing element and the set of second processing elements, as well asbetween the set of second processing elements and the third processingelement.

[0017] Wireless Communications Systems and Methods for ContiguouslyAddressable Memory Enabled Multiple Processor Based Multiple UserDetection

[0018] Another aspect of the invention provides a multiusercommunications device for detecting user transmitted symbols in CDMAshort-code spread spectrum waveforms in which a set of first processingelements generates a matrix (hereinafter the “R-matrix”) that representscross-correlations among user waveforms based on their amplitudes andtime lags. The first processing elements store that matrix to contiguouslocations of an associated memory.

[0019] Further aspects of the invention provide a device as describedabove in which a second processing element, which accesses thecontiguously stored R-matrix, generates estimates of the usertransmitted symbols.

[0020] Still further aspects of the invention provide such a device inwhich a third processing element generates a further matrix(hereinafter, “gamma-matrix”) that represents a correlation between aCDMA short-code associated with one user and those associated with oneor more other users; this gamma-matrix used by the set of firstprocessing elements in generating the R-matrix. In related aspects, theinvention provides such a device in which the third processing elementstores the gamma-matrix to contiguous locations of a further memory.

[0021] In other aspects, the invention provides a multiuser device asdescribed above in which a host controller performs a “partitioningfunction” of the type described above that assigning to each processingelement within the set a portion of the R-matrix to generate. Stillfurther aspects provide such a device in which the host controller iscoupled to the processing elements by way of a multi-port data switch.

[0022] Other aspects of the invention provide such a device in which thethird processing element transfers the gamma-matrix to the set of firstprocessing elements via a memory element.

[0023] Further aspects of the invention provide a multiusercommunications device as described above with a direct memory access(DMA) engine that places elements of the R-matrix into theaforementioned contiguous memory locations.

[0024] Further aspects of the invention provide methods for operating amultiuser communications device paralleling the operations describedabove.

[0025] Wireless Communications Systems and Methods for Cache EnabledMultiple Processor Based Multiple User Detection

[0026] Other aspects of the invention provide a multiuser communicationsdevice that makes novel use of cache and random access memory fordetecting user transmitted symbols in CDMA short-code spectrumwaveforms. According to one such aspect, there is provided a processingelement having a cache memory and a random access memory. A hostcontroller places in the cache memory data representative ofcharacteristics of the user waveforms. The processing element generatesa matrix as a function of the data stored in the cache, and stores thematrix in either the cache or the random access memory.

[0027] Further aspects of the invention provide a device as describedabove in which the host controller stores in cache data representativeof the user waveforms short-code sequences. The processing elementgenerates the matrix as a function of that data, and stores the matrixin random access memory.

[0028] Still further aspects of the invention provide such a device inwhich the host controller stores in cache data representative of acorrelation of time-lags between the user waveforms and datarepresentative of a correlation of complex amplitudes of the userwaveforms. The host controller further stores in random access memorydata representing a correlation of short-code sequences for the userswaveforms. The processing element generates the matrix as a function ofthe data and stores that matrix in RAM.

[0029] Further aspects of the invention provide a device as describedabove in which a host controller stores in cache an attributerepresentative of a user waveform, and stores in random access memory anattributes representing a cross-correlation among user waveforms basedon time-lags and complex amplitudes. The processing element generatesestimates of user transmitted symbols and stores those symbols in randomaccess memory.

[0030] Other aspects of the invention provide such a device in which thehost controller transmits the matrix stored in the cache or randomaccess memory of a processing element to the cache or random accessmemory of a further processing element.

[0031] Further aspects of the invention provide a multiusercommunications device as described above with a multi-port data switchcoupled to a short-code waveform receiver system and also coupled to ahost controller. The host controller routes data generated by thereceiver system to the processing element via the data switch.

[0032] Further aspects of the invention provide methods for operating amultiuser communications device paralleling the operations describedabove.

[0033] Wireless Communications Systems and Methods for NonvolatileStorage of Operating Parameters for Multiple Processor Based MultipleUser Detection

[0034] Another aspect of the invention provides a multiusercommunications device for detecting user transmitted symbols in CDMAshort-code spectrum waveforms in which fault and configurationinformation is stored to a nonvolatile memory. A processing element,e.g. that performs symbol detection, is coupled with random access andnonvolatile memories. A fault monitor periodically polls the processingelement to determine its operational status. If the processing elementis non-operational, the fault monitor stores information includingconfiguration and fault records, as well at least a portion of data fromthe processing element's RAM, into the nonvolatile memory.

[0035] According to further aspects according to the invention,following detection of the non-operational status, the fault monitorsends to a host controller a reset-request interrupt together with theinformation stored in the nonvolatile RAM. In turn, the host controllerselectively issues a reset command to the processing element. In relatedaspects, the processing element resets in response to the reset commandand transfers (or copies) the data from the nonvolatile memory into theRAM, and therefrom continues processing the data in the normal course.

[0036] Further aspects of the invention provide a device as describedabove in which the processing element periodically signals the faultmonitor and, in response, the fault monitor polls the processingelement. If the fault monitor does not receive such signaling within aspecified time period, it sets the operational status of the processingelement to non-operational.

[0037] According to a related aspect of the invention, the fault monitorplaces the processing elements in a non-operational status whileperforming a reset. The fault monitor waits a time period to allow fornormal resetting and subsequently polls the processor to determine itsoperational status.

[0038] Still further aspects of the invention provide a device asdescribed above in which there are a plurality of processing elements,each with a respective fault monitor.

[0039] Yet still further related aspects of the invention provide forthe fault monitoring a data bus coupled with the processing element.

[0040] Further aspects of the invention provide methods for operating amultiuser communications device paralleling the operations describedabove.

[0041] Wireless Communications Systems and Methods for MultipleOperating System Multiple User Detection

[0042] Another aspect of the invention provides a multiusercommunications device for detecting user transmitted symbols in CDMAshort-code spectrum waveforms in which a first process operating under afirst operating system executes a first set of communication tasks fordetecting the user transmitted symbols and a second process operatingunder a second operating system—that differs from the first operatingsystem—executes a second set of tasks for like purpose. A protocoltranslator translates communications between the processes. According toone aspect of the invention, the first process generates instructionsthat determine how the translator performs such translation.

[0043] According to another aspect of the invention, the first processsends a set of instructions to the second process via the protocoltranslator. Those instructions define the set of tasks executed by thesecond process.

[0044] In a related aspect of the invention, the first process sends tothe second process instructions for generating a matrix. That can be,for example, a matrix representing any of a correlation of short-codesequences for the user waveforms, a cross-correlation of the userwaveforms based on time-lags and complex amplitudes, and estimates ofuser transmitted symbols embedded in the user waveforms.

[0045] Further aspects of the invention provide a device as describedabove in which the first process configures the second process, e.g.,via data sent through the protocol translator. This can include, forexample, sending a configuration map that defines where a matrix (orportion thereof) generated by the second process is stored or otherwisedirected.

[0046] Still further aspects of the invention provide a device asdescribed above in which the first process is coupled to a plurality ofsecond processes via the protocol translator. Each of the latterprocesses can be configured and programmed by the first process togenerate a respective portion of a common matrix, e.g., of the typedescribed above. Further aspects of the invention provide methods foroperating a multiuser communications device paralleling the operationsdescribed above.

[0047] Wireless Communications Systems and Methods for Direct MemoryAccess and Buffering of Digital Signals for Multiple User Detection

[0048] Another aspect of the invention provides a multiusercommunications device for detecting user transmitted symbols in CDMAshort-code spectrum waveforms in which a programmable logic device(hereinafter “PLD”) enables direct memory access of data stored in adigital signal processor (hereinafter “DSP”). The DSP has a memorycoupled with a DMA controller that is programmed via a host port. ThePLD programs the DMA controller via the host port to allow a bufferdirect access to the memory.

[0049] In a related aspect according to the invention, the PLD programsthe DMA controller to provide non-fragmented block mode data transfersto the buffer. From the buffer, the PLD moves the blocks to a dataswitch that is coupled to processing devices. In a further relatedaspects according to the invention, the PLD programs the DMA controllerto provide fragmented block mode data transfers utilizing a protocol.The PLD provides the protocol which fragments and unfragments the blocksprior to moving them to the data switch.

[0050] In further aspects provided by a device as described above, thePLD is implemented as a field programmable gate array that is programmedby a host controller coupled with the data switch. In a related aspect,the PLD is implemented as a application specific integrated circuitwhich is programmed during manufacture. In still aspects, a device asdescribed above provides for a buffer implemented as a set of registers,or as dual-ported random access memory.

[0051] Further aspects of the invention provide methods for operating amultiuser communications device paralleling the operations describedabove.

[0052] Improved Wireless Communications Systems and Methods forShort-Code Multiple User Detection

[0053] Still further aspects of the invention provide methods forprocessing short code spread spectrum waveforms transmitted by one ormore users including the step of generating a matrix indicative of crosscorrelations among the waveforms as a composition of (i) a firstcomponent that represents correlations among time lags and short codesassociated with the waveforms transmitted by the users, and (ii) asecond component that represents correlations among multipath signalamplitudes associated with the waveforms transmitted by the users. Themethod further includes generating detection statistics corresponding tothe symbols as a function of the correlation matrix, and generatingestimates of the symbols based on those detection statistics.

[0054] Related aspects of the invention provided methods as describedabove in which the first component is updated on a time scale that iscommensurate with a rate of change of the time lags associated with thetransmitted waveforms, and the second component is updated on adifferent time scale, i.e., one that is commensurate with a rate ofchange of the multipath amplitudes associated with these waveforms. Inmany embodiments, the updating of the second component, necessitated asa result of change in the multipath amplitudes, is executed on a shortertime scale than that of updating the first component.

[0055] Other aspects of the invention provide methods as described abovein which the first component of the cross-correlation matrix isgenerated as a composition of a first matrix component that isindicative of correlations among the short codes associated with therespective users, and a second matrix component that is indicative ofthe waveforms transmitted by the users and the time lags associated withthose waveforms.

[0056] In a related aspect, the invention provides methods as above inwhich the first matrix component is updated upon addition or removal ofa user to the spread spectrum system. This first matrix component(referred to below as Γ-matrix) can be computed as a convolution of theshort code sequence associated with each user with the short codes ofother users.

[0057] According to further aspects of the invention, elements of theΓ-matrix are computed in accord with the relation:${\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n = 0}^{N - 1}{{c_{i}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}$

[0058] wherein

[0059] c_(l)*[n] represents the complex conjugate of a short codesequence associated with the l^(th) user,

[0060] c_(k)[n−m] represents a short code sequence associated with thek^(th) user,

[0061] N represents a length of the short code sequence, and

[0062] N_(l) represent a number of non-zero length of the short codesequence.

[0063] In further aspects, the invention provides a method as describedabove in which the first component of the cross-correlation matrix(referred to below as the C matrix) is obtained as a function of theaforementioned Γ-matrix in accord with the relation:${C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack} = {\sum\limits_{m}{{g\left\lbrack {{mN}_{c} + \tau} \right\rbrack} \cdot {\Gamma_{lk}\lbrack m\rbrack}}}$

[0064] wherein

[0065] g is a pulse shape vector,

[0066] Nc is the number of samples per chip,

[0067] τ is a time lag, and

[0068] Γ represents the Γ matrix, e.g., defined above.

[0069] In a related aspect, the cross-correlation matrix (referred tobelow as the R-matrix) can be generated as a function of the C matrix inaccord with the relation:${r_{lk}\left\lbrack m^{\prime} \right\rbrack} = {{\sum\limits_{q = 1}^{L}{\sum\limits_{q^{\prime} = 1}^{L}{{Re}\left\{ {{\hat{a}}_{lq}^{*}{a_{{kq}^{\prime}} \cdot {C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack}}} \right\}}}} = {{Re}\left\{ {a_{l}^{H} \cdot {C_{lk}\left\lbrack m^{\prime} \right\rbrack} \cdot a_{k}} \right\}}}$

[0070] wherein

[0071] â_(lq)* is an estimate of a_(lq)*, the complex conjugate of onemultipath amplitude component of the l^(th) user,

[0072] a_(kq), is one multipath amplitude component associated with thek^(th) user, and

[0073] C denotes the C matrix, e.g., as defined above.

[0074] In further aspects, the invention provides methods as describedabove in which the detection statistics are obtained as a function ofthe cross-correlation matrix (e.g., the R-matrix) in accord with therelation: $\begin{matrix}{{y_{l}\lbrack m\rbrack} = {{{r_{ll}\lbrack 0\rbrack}{b_{l}\lbrack m\rbrack}} + {\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\left\lbrack {- 1} \right\rbrack}{b_{k}\left\lbrack {m + 1} \right\rbrack}}} +}} \\{{{\sum\limits_{k = 1}^{K_{v}}{\left\lbrack {{r_{lk}\lbrack 0\rbrack} - {{r_{ll}\lbrack 0\rbrack}\delta_{lk}}} \right\rbrack {b_{k}\lbrack m\rbrack}}} +}} \\{{\sum\limits_{k = 1}^{K_{v}}\left\lbrack {{{r_{lk}\lbrack 1\rbrack}{b_{k}\left\lbrack {m - 1} \right\rbrack}} + {\eta_{l}\lbrack m\rbrack}} \right.}}\end{matrix}$

[0075] wherein

[0076] y_(l)[m] represents a detection statistic corresponding to m^(th)symbol transmitted by the l^(th) user,

[0077] r_(ll)[0]b_(l)[m] represents a signal of interest, and

[0078] remaining terms of the relation represent Multiple AccessInterference (MAI) and noise.

[0079] In a related aspect, the invention provides methods as describedabove in which estimates of the symbols transmitted by the users andencoded in the short code spread spectrum waveforms are obtained basedon the computed detection statistics by utilizing, for example, amulti-stage decision-feedback interference cancellation (MDFIC) method.Such a method can provide estimates of the symbols, for example, inaccord with the relation: $\begin{matrix}{{{\hat{b}}_{l}\lbrack m\rbrack} = {{sign}\left\{ {{y_{l}\lbrack m\rbrack} - {\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\left\lbrack {- 1} \right\rbrack}{{\hat{b}}_{k}\left\lbrack {m + 1} \right\rbrack}}} -} \right.}} \\{{{\sum\limits_{k = 1}^{K_{v}}{\left\lbrack {{r_{lk}\lbrack 0\rbrack} - {{r_{ll}\lbrack 0\rbrack}\delta_{lk}}} \right\rbrack {{\hat{b}}_{k}\lbrack m\rbrack}}} -}} \\{\left. {\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\lbrack 1\rbrack}{{\hat{b}}_{k}\left\lbrack {m - 1} \right\rbrack}}} \right\}}\end{matrix}$

[0080] wherein

[0081] {circumflex over (b)}_(l)[m] represents an estimate of the m^(th)symbol transmitted by the l^(th) user.

[0082] Further aspects of the invention provide logic carrying outoperations paralleling the methods described above.

[0083] Load Balancing Computational Methods in a Short-CodeSpread-Spectrum Communications System

[0084] In further aspects, the invention provides methods for computingthe cross-correlation matrix described above by distributing among aplurality of logic units parallel tasks—each for computing a portion ofthe matrix. The distribution of tasks is preferably accomplished bypartitioning the computation of the matrix such that the computationalload is distributed substantially equally among the logic units.

[0085] In a related aspect, a metric is defined for each partition inaccord with the relation below. The metric is utilized as a measure ofthe computational load associated with each logic unit to ensure thatthe computational load is distributed substantially equally among thelogic units:

B _(i) =A _(i) −A _(i)−1

[0086] wherein

[0087] A_(i) represents an area of a portion of the cross-correlationmatrix corresponding to the i^(th) partition, and

[0088] i represents an index corresponding to the number of logic unitsover which the computation is distributed.

[0089] In another aspect, the invention provides methods as describedabove in which the cross-correlation matrix is represented as acomposition of a rectangular component and a triangular component. Eacharea, represented by A_(i) in the relation above, includes a firstportion corresponding to the rectangular component and a second portioncorresponding to the triangular component.

[0090] Further aspects of the invention provide logic carrying outoperations paralleling the methods described above.

[0091] Hardware and Software for Performing Computations in a Short-CodeSpread-Spectrum Communications System

[0092] In other aspects, the invention provides an apparatus forefficiently computing a Γ-matrix as described above, e.g., in hardware.The system includes two registers, one associated with each of l^(th)and k^(th) users. The registers hold elements of the short codesequences associated with the respective user such that alignment of theshort code sequence loaded in one register can be shifted relative tothat of the other register by m elements. Associated with each of theforegoing registers is one additional register storing mask sequences.Each element in those sequences is zero if a corresponding element ofthe short code sequence of the associated register is zero and,otherwise, is non-zero. The mask sequences loaded in these furtherregisters are shifted relative to the other by m elements. A logicperforms an arithmetic operation on the short code and mask sequences togenerate, for m^(th) transmitted symbol, the (l, k) element of theΓ-matrix, i.e., Γ_(lk)[m]

[0093] In a related aspect, the invention provides an apparatus asdescribed above in which the arithmetic operation performed by the logicunit includes, for any two aligned elements of the short code sequencesof the l^(th) and k^(th) user and the corresponding elements of the masksequences, (i) an XOR operation between the short code elements, (ii) anAND operation between the mask elements, (iii) an AND operation betweenresults of the step (i) and step (ii). The result of step (iii) is amultiplier for the aligned elements, which the logic sums in order togenerate the (l, k) element of the Γ-matrix.

[0094] Further aspects of the invention provide methods paralleling theoperations described above.

[0095] Improved Computational Methods for Use in a Short-CodeSpread-Spectrum Communications System

[0096] In still further aspects, the invention provides improvedcomputational methods for calculating the aforesaid cross-correlationmatrix by utilizing a symmetry property. Methods according to thisaspect include computing a first one of two matrices that are related bya symmetry property, and calculating a second one of the two matrices asa function of the first component through application of the symmetryproperty.

[0097] According to related aspects of the invention, the symmetryproperty is defined in accord with the relation:

R _(lk)(m)=ξR _(k,l)(−m)

[0098] wherein

[0099] R_(lk)(m) and R_(kl)(m) refer to (l, k) and (k, l) elements ofthe cross-correlation matrix, respectively.

[0100] Further aspects of the invention provide methods as describedabove in which calculation of the cross-correlation matrix furtherincludes determining a C matrix that represents correlations among timelags and short codes associated with the waveforms transmitted by theusers, and an R-matrix that represents correlations among multipathsignal amplitudes associated with the waveforms transmitted by theusers. In related aspects the step of determining the C matrix includesgenerating a first of two C-matrix components related by a symmetryproperty. A second of the components is then generated by applying thesymmetry property.

[0101] Related aspects of the invention provide a method as describedabove including the step of generating the Γ-matrix in accord with therelation:${\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n = 0}^{N - 1}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}$

[0102] wherein

[0103] c_(l)*[n] represents complex conjugate of the short code sequenceassociated with the lth user,

[0104] c_(k)[n−m] represents the short code sequence associated with kthuser,

[0105] N represents the length of the code, and

[0106] N_(l) represent the number of non-zero length of the code.

[0107] Further aspects of the invention provide logic carrying outoperations paralleling the methods described above.

[0108] Wireless Communications Systems and Methods for Virtual UserBased Multiple User Detection Utilizing Vector Processor GeneratedMapped Cross-Correlation Matrices

[0109] Still further aspects of the invention provide methods fordetecting symbols encoded in physical user waveforms, e.g., thoseattributable to cellular phones, modems and other CDMA signal sources,by decomposing each of those waveforms into one or more respectivevirtual user waveforms. Each waveform of this latter type represents atleast a portion of a symbol encoded in the respective physical userwaveforms and, for example, can be deemed to “transmit” a single bit persymbol period. Methods according to this aspect of the inventiondetermine cross-correlations among the virtual user waveforms as afunction of one of more characteristics of the respective physical userwaveforms. From those cross-correlations, the methods generate estimatesof the symbols encoded in the physical user waveforms.

[0110] Related aspects of the invention provide methods as describedabove in which a physical user waveforms is decomposed into a virtualuser waveform that represents one or more respective control or databits of a symbol encoded in the respective physical user waveform.

[0111] Other related aspects provide for generating thecross-correlations in the form of a first matrix, e.g., an R-matrix forthe virtual user waveforms. That matrix can, according to still furtherrelated aspects of the invention, be used to generate a second matrixrepresenting cross-correlations of the physical user waveforms. Thissecond matrix is generated, in part, as a function of a vectorindicating the mapping of virtual user waveforms to physical userwaveforms.

[0112] Further aspects of the invention provide a system for detectingsymbols encoded in physical user waveforms that has multiple processors,e.g., each with an associated vector processor, that operates in accordwith the foregoing methods to generate estimates of the symbols encodedin the physical user waveforms.

[0113] Still other aspects of the invention provide a system fordetecting user transmitted symbols encoded in short-code spread spectrumwaveforms that generates cross-correlations among the waveforms as afunction of block-floating integer representations of one or morecharacteristics of those waveforms. Such a system, according to relatedaspects of the invention, utilizes a central processing unit to formfloating-point representations of virtual user waveform characteristicsinto block-floating integer representations. A vector processor,according to further related aspects, generates the cross-correlationsfrom the latter representations. The central processing unit can“reformat” the resulting block-floating point matrix into floating-pointformat, e.g., for use in generating symbol estimates.

[0114] Still further aspects of the invention provide methods andapparatus employing any and all combinations of the foregoing. These andother aspects of the invention, which includes combinations of theforegoing, are evident in the illustrations and in the text thatfollows.

BRIEF DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

[0115] A more complete understanding of the invention may be attained byreference to the drawings, in which:

[0116]FIG. 1 is a block diagram of components of a wireless base-stationutilizing a multi-user detection apparatus according to the invention;

[0117]FIG. 2 is a block diagram of components of a multiple userdetection processing card according to the invention;

[0118]FIG. 3 is a more detailed view of the processing board of FIG. 2;

[0119]FIG. 4 depicts a majority-voter sub-system in a system accordingto the invention;

[0120]FIG. 5 is a block diagram of an integrated direct memory access(DMA) engine of the type used in a system according to the invention;

[0121]FIGS. 6 and 7 depict power on/off curves for the processor boardin a system according to the invention;

[0122]FIG. 8 are an operational overview of functionality within thehost processor and multiple compute nodes in a system according to theinvention;

[0123]FIG. 9 is a block diagram of an external digital signal processorapparatus used to supply digital signals to the processor board in asystem according to the invention;

[0124]FIG. 10 illustrates an example of loading the R matrices onmultiple compute nodes in a system according to the invention;

[0125]FIG. 11 depicts a short-code loading implementation with parallelprocessing of the matrices in a system according to the invention;

[0126]FIG. 12 depicts a long-code loading implementation utilizingpipelined processing and a triple-iteration of refinement in a systemaccording to the invention;

[0127]FIG. 13 illustrates skewing of multiple user waveforms;

[0128]FIG. 14 is a graph illustrating MUD efficiency as a function ofuser velocity in units of Km/hr.

[0129]FIG. 15 schematically illustrates a method for defining a commoninterval for three short-code streams utilized in a FFT calculation ofthe Γ-matrix;

[0130]FIG. 16 schematically illustrates the Γ-matrix elements calculatedupon addition of a new physical user to a system according to theinvention;

[0131]FIGS. 17, 18 and 19 depict hardware calculation of the Γ-matrix ina system according to the invention;

[0132]FIG. 20 illustrates parallel computation of the R and C matricesin a system according to the invention;

[0133]FIG. 21 depicts a use of a vector processor using integer operandsfor generating a cross-correlation matrix of virtual user waveforms in asystem according to the invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

[0134] Code-division multiple access (CDMA) waveforms or signalstransmitted, e.g., from a user cellular phone, modem or other CDMAsignal source, can become distorted by, and undergo amplitude fades andphase shifts due to phenomena such as scattering, diffraction and/orreflection off buildings and other natural and man-made structures. Thisincludes CDMA, DS/CDMA, IS-95 CDMA, CDMAOne, CDMA2000 1X, CDMA20001xEV-DO, WCDMA (or UTMS), and other forms of CDMA, which arecollectively referred to hereinafter as CDMA or WCDMA. Often the user orother source (collectively, “user”) is also moving, e.g., in a car ortrain, adding to the resulting signal distortion by alternatelyincreasing and decreasing the distances to and numbers of building,structures and other distorting factors between the user and the basestation.

[0135] In general, because each user signal can be distorted severaldifferent ways en route to the base station or other receiver(hereinafter, collectively, “base station”), the signal may be receivedin several components, each with a different time lag or phase shift. Tomaximize detection of a given user signal across multiple tag lags, arake receiver is utilized. Such a receiver is coupled to one or more RFantennas (which serve as a collection point(s) for the time-laggedcomponents) and includes multiple fingers, each designed to detect adifferent multipath component of the user signal. By combining thecomponents, e.g., in power or amplitude, the receiver permits theoriginal waveform to be discerned more readily, e.g., by downstreamelements in the base station and/or communications path.

[0136] A base station must typically handle multiple user signals, anddetect and differentiate among signals received from multiplesimultaneous users, e.g., multiple cell phone users in the vicinity ofthe base station. Detection is typically accomplished through use ofmultiple rake receivers, one dedicated to each user. This strategy isreferred to as single user detection (SUD). Alternately, one largerreceiver can be assigned to demodulate the totality of users jointly.This strategy is referred to as multiple user detection (MUD). Multipleuser detection can be accomplished through various techniques which aimto discern the individual user signals and to reduce signal outageprobability or bit-error rates (BER) to acceptable levels.

[0137] However, the process has heretofore been limited due tocomputational complexities which can increase exponentially with respectto the number of simultaneous users. Described below are embodimentsthat overcome this, providing, for example, methods for multiple userdetection wherein the computational complexity is linear with respect tothe number of users and providing, by way of further example, apparatusfor implementing those and other methods that improve the throughput ofCDMA and other spread-spectrum receivers. The illustrated embodimentsare implemented in connection with short-code CDMA transmitting andreceiver apparatus; however those skilled in the art will appreciatethat the methods and apparatus therein may be used in connection withlong-code and other CDMA signalling protocols and receiving apparatus,as well as with other spread spectrum signalling protocols and receivingapparatus. In these regards and as used herein, the terms long-code andshort-code are used in their conventional sense: the former referring tocodes that exceed one symbol period; the latter, to codes that are asingle symbol period or less.

[0138]FIG. 1 depicts components of a wireless base station 100 of thetype in which the invention is practiced. The base station 100 includesan antenna array 114, radio frequency/intermediate frequency (RF/IF)analog-to-digital converter (ADC), multi-antenna receivers 110, rakemodems 112, MUD processing logic 118 and symbol rate processing logic120, coupled as shown.

[0139] Antenna array 114 and receivers 110 are conventional such devicesof the type used in wireless base stations to receive wideband CDMA(hereinafter “WCDMA”) transmissions from multiple simultaneous users(here, identified by numbers 1 through K). Each RF/IF receiver (e.g.,110) is coupled to antenna or antennas 114 in the conventional mannerknown in the art, with one RF/IF receiver 110 allocated for each antenna114. Moreover, the antennas are arranged per convention to receivecomponents of the respective user waveforms along different laggedsignal paths discussed above. Though only three antennas 114 and threereceivers 110 are shown, the methods and systems taught herein may beused with any number of such devices, regardless of whether configuredas a base station, a mobile unit or otherwise. Moreover, as noted above,they may be applied in processing other CDMA and wireless communicationssignals.

[0140] Each RF/IF receiver 110 routes digital data to each modem 112.Because there are multiple antennas, here, Q of them, there aretypically Q separate channel signals communicated to each modem card112.

[0141] Generally, each user generating a WCDMA signal (or other subjectwireless communication signal) received and processed by the basestation is assigned a unique short-code code sequence for purposes ofdifferentiating between the multiple user waveforms received at thebasestation, and each user is assigned a unique rake modem 112 forpurposes of demodulating the user's received signal. Each modem 112 maybe independent, or may share resources from a pool. The rake modems 112process the received signal components along fingers, with each receiverdiscerning the signals associated with that receiver's respective usercodes. The received signal components are denoted here as r_(kq)[t]denoting the channel signal (or waveform) from the k^(th) user from theq^(th) antenna, or r_(k)[t] denoting all channel signals (or waveforms)originating from the k^(th) user, in which case r_(k)[t] is understoodto be a column vector with one element for each of the Q antennas. Themodems 112 process the received signals r_(k)[t] to generate detectionstatistics y_(k) ⁽⁰⁾[m] for the k^(th) user for the mth symbol period.To this end, the modems 122 can, for example, combine the componentsr_(kq)[t] by power, amplitude or otherwise, in the conventional mannerto generate the respective detection statistics y_(k) ⁽⁰⁾[m]. In thecourse of such processing, each modem 112 determines the amplitude(denoted herein as a) of and time lag (denoted herein as τ) between themultiple components of the respective user channel. The modems 112 canbe constructed and operated in the conventional manner known in the art,optionally, as modified in accord with the teachings of some of theembodiments below.

[0142] The modems 112 route their respective user detection statisticsy_(k) ⁽⁰⁾[m], as well as the amplitudes and time lags, to common userdetection (MUD) 118 logic constructed and operated as described in thesections that follow. The MUD logic 118 processes the received signalsfrom each modem 112 to generate a refined output, y_(k) ⁽¹⁾[m], or moregenerally, y_(k) ^((n))[m], where n is an index reflecting the number oftimes the detection statistics are iteratively or regenerativelyprocessed by the logic 118. Thus, whereas the detection statisticproduced by the modems is denoted as y_(k) ⁽⁰⁾[m] indicating that therehas been no refinement, those generated by processing the y_(k) ⁽⁰⁾[m]detection statistics with logic 118 are denoted y_(k) ⁽¹⁾[m], thosegenerated by processing the y_(k) ⁽¹⁾[m] detection statistics with logic118 are denoted y_(k) ⁽²⁾[m], and so forth. Further waveforms used andgenerated by logic 118 are similarly denoted, e.g., r^((n))[t].

[0143] Though discussed below are embodiments in which the logic 118 isutilized only once, i.e., to generate y_(k) ⁽¹⁾[m] from y_(k) ⁽⁰⁾[m],other embodiments may employ that logic 118 multiple times to generatestill more refined detection statistics, e.g., for wirelesscommunications applications requiring lower bit error rates (BER). Forexample, in some implementations, a single logic stage 118 is used forvoice applications, whereas two or more logic stages are used for dataapplications. Where multiple stages are employed, each may be carriedout using the same hardware device (e.g., processor, co-processor orfield programmable gate array) or with a successive series of suchdevices.

[0144] The refined user detection statistics, e.g., y_(k) ⁽¹⁾[m] or moregenerally y_(k) ^((n))[m], are communicated by the MUD process 118 to asymbol process 120. This determines the digital information containedwithin the detection statistics, and processes (or otherwise directs)that information according to the type of user class for which the userbelongs, e.g., voice or data user, all in the conventional manner.

[0145] Though the discussion herein focuses on use of MUD logic 118 in awireless base station, those skilled in the art will appreciate that theteachings hereof are equally applicable to MUD detection in any otherCDMA signal processing environment such as, by way of non-limitingexample, cellular phones and modems. For convenience, such cellular basestations other environments are referred to herein as “base stations.”Multiple User Detection Processing Board

[0146]FIG. 2 depicts a multiple user detection (MUD) processing cardaccording to the invention. The illustrated processing card 118 includesa host processor 202, an interface block 204, parallel processors 208, afront panel device 210, and a multi-channel cross-over device 206(hereinafter “Crossbar”). Although these components are shown asseparate entities, one skilled in the art can appreciate that differentconfigurations are possible within the spirit of the invention. Forexample, the host processor 202 and the interface block 204 can beintegrated into a single assemble, or multiple assemblies.

[0147] The processing card 118 processes waveform and waveformcomponents received by a base station, e.g., from a modem card 112 orreceiver 110 contained within the base station, or otherwise coupledwith the base station. The waveform typically includes CDMA waveforms,however the processing card 118 can also be configured for otherprotocols, such as TDMA and other multiple user communicationtechniques. The processing card 118 performs multiple user detection(MUD) on the waveform data, and generates a user signal corresponding toeach user, with includes less interference than within the receivedsignals.

[0148] The illustrated processing card 118 is a single board assemblyand is manufactured to couple (e.g., electrically and physically mate)with a conventional base station (e.g., a modem card 112, receiver 110or other component). The board assembly illustrated conforms to a ¾ formfactor modem payload card of the type available in the marketplace. Theprocessor card 118 is designed for retrofitting into existing basestations or for design into new station equipment. In other embodiments,the processing card can be either single or multiple assemblies.

[0149] The host processor 202 routes data from the interface block 204to and among the parallel processors 208, as well as performs faultmonitoring and automated resets, data transfer, and processor loading ofthe parallel processors 208. The host processor 202 also processesoutput received from the parallel processors 208, and communicates theprocessed output to the interface block 204 for subsequent return to thebase station.

[0150] The parallel processors 202 process waveforms and waveformcomponents routed from the host processor 206. Typically, the parallelprocessors 202 process the waveform components, and communicate theprocessed data back to the host processor 202 for further processing andsubsequent transmission to the base station, however, the intermediateprocessed waveforms can be communicated to other parallel processors ordirectly to the base station.

[0151] The crossbar 206 is a communication switch which routes messagesbetween multiple devices. It allows multiple connection data ports to beconnection with other data ports. In the illustrated embodiment, thecrossbar 206 provides eight ports, where a port can be “connected” toany other port (or to multiple ports) to provide communication betweenthose two (or indeed, multiple) ports. Here, the crossbar 206 is aRACEway™ switch of the type commercially available from the assigneehereof. In other embodiments, other switching elements, whetherutilizing the RACEway™ protocol or otherwise, may be used, e.g., PCI,12C and so on. Indeed, in some embodiments, the components communicatealong a common bus and/or are distributed via over a network.

[0152] A front panel 210 is used to monitor the processor card and canbe used to apply software patches, as well as perform other maintenanceoperations. Additionally, the front panel 210 can be used to monitorfault status and interface connections through a series of LEDindicators, or other indicators. Illustrated front panel interfaces withthe board via the RACEway™ switch and protocol, though other interfacetechniques may be used as well.

[0153]FIG. 3 depicts further details of the processor card of FIG. 2.The illustrated processor card includes a host processor 202 incommunication with an interface block 205 and a set of parallelprocessors 208 (hereinafter “compute elements”) as described above, aswell as a crossbar 206 and a front panel 210. Further, a powerstatus/control device 240 is assembled on the processor card 118.However, in other embodiments, the power status/control device 240 canbe within the base station or elsewhere.

[0154] The host processor 202 includes a host controller 203 with anintegrated processor containing a peripheral logic block and a 32-bitprocessor core. The host controller 203 is coupled with various memorydevices 205, a real time clock 206, and a protocol translator 208. Inthe illustrated embodiment, the host controller 203 can be a MotorolaPowerPC 8240 commercially available, but it will be appreciated by oneskilled in the art that other integrated processors (or evennon-integrated processors) can be used which satisfy the requirementsherein.

[0155] The host controller 203 controls data movement within theprocessor card 118 and between the processor card and the base station.It controls the crossbar device 206 by assigning the connection betweenconnection ports. Further, the host controller 203 applies functionalityto the output generated by the parallel processors 208. The hostcontroller 203 includes a monitor/watchdog sub-system which monitors theperform ace of the various components within the processor card, and canissue resets to the components. In some embodiments, these functions canbe provided (or otherwise assisted) by application specific integratedcircuits or field programmable gate arrays.

[0156] The host controller 203 integrates a PCI bus 211 a, 211 b fordata movement with the memory devices 205 and the interface block 205,as well as other components. The PCI bus 211 a, 211 b is capable of32-bit or 64-bit data transfers operating at 33 MHz, or alternatively 66MHz speeds, and supports access to PCI memory address spaces usingeither (or both) little and/or big endian protocols.

[0157] Memory devices used by the host controller 203 include HARegisters 212, synchronous dynamic random access memory (SDRAM) 214,Flash memory 216, and Non-Volatile Ram (NVRAM) 218. As will be evidentbelow, each type of memory is used for differing purposes.

[0158] The HA registers 212 store operating status (e.g., faults) forthe parallel processors 208, the power status/control device 240, andother components. A fault monitoring sub-system “watchdog” writes bothsoftware and hardware status into the HA registers 212, from which thehost controller 203 monitors the registers 212 to determine theoperational status of the components. The HA registers 212 are mappedinto banked memory locations, and are thereby addressable as directaccess registers. In some embodiments, the HA registers 212 can beintegrated with the host controller 203 and still perform the samefunction.

[0159] The SDRAM 214 stores temporary application and data. In theillustrated embodiment, there is 64 Kbytes of SDRAM 214 available tosupport transient data, e.g., intermediary results from processing andtemporary data values. The SDRAM 214 is designed to be directly accessedby the host controller 203 allowing for fast DMA transfers.

[0160] The flash memory 216 includes two Intel StrataFlash devices,although equivalent memory devices are commercially available. It storesdata related to component performance data, and intermediate data whichcan be used to continue operation after resets are issued. The flashmemory is blocked at 8 Kbyte boundaries, but in other embodiments, theblock size can vary depending on the addressing capabilities of the hostcontroller 203 and method of communication with the memory devices.Further, because flash memory requires no power source to retainprogrammed memory data, its data can be used for diagnostic purposeseven in the event of power-failures.

[0161] NVRAM is, to an extent, reserved for fault record data andconfiguration information. Data stored within the NVRAM 218, togetherwith the flash memory 216 is sufficient to reproduce the data within theSDRAM 218 upon system (or board level, or even component level) reset.If a component is reset during operation, the host controller 203 cancontinue operation without the necessity of receiving additionalinformation from the base station via the data stored in the NVRAM. TheNVRAM 218 is coupled to the host controller 203 via a buffer whichconverts the voltage of the PCI bus 211 a from 3.3v to 5v, as requiredby the NVRAM 218, however this conversion is not necessary in otherembodiments with different memory configurations.

[0162] The interface block 205 includes a PCI bridge 222 incommunication with an Ethernet interface 224 and a modem connection 226.The PCI bridge 222 translates data received from the PCI bus 211 b intoa protocol recognized by the base station modem card 112. Here, themodem connection 226 operates with a 32-bit interface operating at 66MHz, however, in other embodiments the modem can operate with differentcharacteristics. The Ethernet connection 224 can operate at either 10Mbytes/Sec or 100 Mbytes/Sec, and is therefore suited for most Ethernetdevices. Those skilled in the art can appreciate that these interfacedevices can be interchanged with other interface devices (e.g., LAN,WAN, SCSI and the like).

[0163] The real-time clock 206 supplies timing for the host controller203 and the parallel processors 208, and thus, synchronizes datamovement within the processing card. It is coupled with the hostcontroller 203 via an integrated I2C bus (as established by PhillipsCorporation, although in other embodiments the clock can be connectedvia other electrical coupling). The real-time clock 206 is implementedas a CMOS device for low power consumption. The clock generates signalswhich control address and data transfers within the host controller 203and the multiple processors 208.

[0164] A protocol converter 208 (hereinafter “PXB”) converts PCIprotocol used by the host controller 203 to RACEway™ protocol used bythe parallel processors 208 and front panel 210. The PXB 208 contains afield programmable gate array (“FPGA”) and EEPROM which can beprogrammed from the PCI bus 211 b. In some embodiments, the PXB 208 isprogrammed during manufacture of the processing card 118 to containconfiguration information for the related protocols and/or componentswith which it communicates. In other embodiments, the PXB 208 can useother protocols as necessary to communicate with the multiple processors208. Of course, if the host controller 203 and the multiple processors208 use the same protocol, there is no protocol conversion necessary andtherefore the PXB is not required.

[0165] The multiple-port communication device 206 (hereinafter“crossbar”) provides communication between all processing andinput/output elements on the processing card 118. In the illustratedembodiment, the crossbar 206 is an EEPROM device which can be read andprogrammed by a RACEway™ compatible component (e.g., the front panel 210or parallel processors 208), but it is typically programmed initiallyduring manufacture. An embedded ASIC device controls the EEPROMprogramming, and hence, the function of the crossbar 206.

[0166] The crossbar 206 in the illustrated provides up to threesimultaneous 266-Mbytes/Sec throughput data paths between elements for atotal throughput of 798 Mbytes/Sec, however, in other embodiments theactual throughput varies according to processing speed. Here, twocrossbar ports (e.g., ports 0 and 1) connect to a bridge FPGA whichfurther connect to the front panel 210. Each of the multiple processorsuse an crossbar port (e.g., ports 2, 3, 5, and 6), and the interfaceblock 224 and host controller 203 share one crossbar port (e.g., port 4)via the PXB 206. The number of ports on the crossbar 206 depends on thenumber of parallel processors and other components that are incommunication.

[0167] The multiple processors 208 in the illustrated embodiment includefour compute elements 220 a-220 d (hereinafter, reference to element 220refers to a general compute element, also referred to herein as a“processing element” or “CE”). Each processing element 220 appliesfunctionality on data, and generates processed date in the form of amatrix, vector, or waveform. The processing elements 220 can alsogenerate scalar intermediate values. Generated data is passed to thehost controller 208, or to other processing elements 220 for furtherprocessing. Further, individual processing elements can be partitionedto operate in series (e.g., as a pipeline) or in parallel with the otherprocessing elements.

[0168] A processing element 220 includes a processor 228 coupled with acache 230, a Joint Test Action Group (hereinafter “JTAG”) interface 232with an integrated programming port, and an application specificintegrated circuit 234 (hereinafter “ASIC”). Further, the ASIC 234 iscoupled with a 128 Mbyte SDRAM device 236 and HA Registers 238. The HARegisters are coupled with 8 Kbytes of NVRAM 244. In the illustratedembodiment the compute elements 220 are on the same assembly as the hostcontroller 203. In other embodiments, the compute nodes 220 can beseparate from the host controller 203 depending on the physical andelectrical characteristics of the target base station.

[0169] The compute node processors 228 illustrated are Motorola PowerPC7400, however in other embodiments the processor can be other processordevices. Each processor 228 uses the ASIC 234 to interface with aRACEway™ bus 246. The ASIC 234 provides certain features of a computenode 220, e.g., a DMA engine, mail box interrupts, timers, page mappingregisters, SDRAM interface and the like. In the illustrated embodimentthe ASIC is programmed during manufacture, however, it can also beprogrammed in the field, or even at system reset in other embodiments.

[0170] The cache 230 for each compute node 220 stores matrices that areslow-changing or otherwise static in relation to other matrices. Thecache 230 is pipelined, single-cycle deselect, synchronous burst staticrandom access memory, although in other embodiments high-speed RAM orsimilar devices can be used. The cache 230 can be implemented usingvarious devices, e.g., multiple 64 Kbyte devices, multiple 256 Kbytedevices, and so on.

[0171] Architecture Pairing of Processing Nodes with NVRAM and Watchdog;Majority Voter

[0172] The HA registers 238 store fault status for the software and/orhardware of the compute element 220. As such, it responds to thewatchdog fault monitor which also monitors the host controller 203 andother components. The NVRAM 244 is, much like the NVRAM coupled with thehost controller 203, stores data from which the current state of thecompute element 220 can be recreated should a fault or reset occur. TheSDRAM 236 is used for intermediate and temporary data storage, and isdirectly addressable from both the ASIC 234 and the processor 228. Thesememory devices can be other devices in other embodiments, depending onspeed requirements, throughput and computational complexity of themultiple user detection algorithms.

[0173] NVRAM is also used to store computational variables and data suchthat upon reset of the processing element or host controller, executioncan be re-started without the need to re-fresh the data. Further, thecontents of NVRAM can be used to diagnose fault states and/orconditions, thus aiding to a determination of the cause of fault state.

[0174] As noted above, a “watchdog” monitors performance of theprocessing card 118. In the illustrated embodiment, there are fiveindependent “watchdog” monitors on the processing card 118 (e.g., onefor the host controller 203 and one each for each compute node 220 a-220d, and so on). The watchdog also monitors performance of the PCI bus aswell as the RaceWay bus connected with each processing element and thedata switch. The RACEWay bus includes out-of-band fault managementcoupled with the watchdogs.

[0175] Each component periodically strobes its watchdog at least every20 msec but not faster that 500 microseconds (these timing parametersvary among embodiments depending on overall throughput of the componentsand clock speed). The watchdog is initially strobed approximately twoseconds after the initialization of a board level reset, which allowsfor start-up sequencing of the components without cycling erroneousresets. Strobing the watchdog for the processing nodes is accomplishedby writing a zero or a one sequence to a discrete word (e.g., within theHA Register 212) originating within each compute element 220 a-220 d,the host controller 203, and other components). The watchdog for thehost controller 203 is serviced by writing to the memory mapped discretelocation FFF_D027 which is contained within the HA Registers 212.

[0176] The watchdog uses five 8-bit status registers within the HAregisters 212, and additional registers (e.g., HA registers 238) withineach compute node 220. One register represents the host controller 203status, and the other four represent each compute node 220 a-220 dstatus. Each register has a format as follows: Bit Name Description 0CHECKSTOP_OUT Checkstop state of CPU (0 = CPU in checkstop) 1 WDM_FAULTWDM failed (0 = WDM failed, set high after reset and valid service) 2SOFTWARE_FAULT Software fault detected (Set to 0 when a soft- wareexception was detected) (R/W local) 3 RESETREQ_IN Wrap status of thelocal CPU's reset request 4 WDM_INIT WDM failed in initial 2 secondwindow (0 = WDM failed) 5 Software definable 0 Software definable 0 6Software definable 1 Software definable 1 7 Unused Unused

[0177] The five registers reflect status information for all processorswithin the processing board 118, and allow the host controller 203 toobtain status of each without the need for polling the processorindividually (which would degrade performance and throughput).Additionally, the host controller 203 and each compute node processor228 has a fault control register which contains fault data according tothe following format: Bit Name Description 0 RESETREQ_OUT_0 Request areset event (0 => forces reset) 1 CHKSTOPOUT_0 Request that node 0 entercheckstop state (0 => request checkstop) 2 CHKSTOPOUT_1 Request thatnode 1 enter checkstop state (0 => request checkstop) 3 CHKSTOPOUT_2Request that node 2 enter checkstop state (0 => request checkstop) 4CHKSTOPOUT_3 Request that node 3 enter checkstop state (0 => requestcheckstop) 5 CHKSTOPOUT_8240 Request that the host controller entercheck- stop state (0 => request checkstop) 6 Software definable 0Software definable 0 7 Software definable 1 Sofiware definable 1

[0178] A single write of any value will strobe the watchdog. Upon eventssuch as power-up, the watchdogs are initialized to a fault state. Once avalid strobe is issued, the watchdog executes and, if all elements areproperly operating, writes a no-fault state to the HA register 212. Thisoccurs within the initial two-second period after board level reset. Ifa processor node fails to service the watchdog within the valid timeframe, the watchdog records a fault state. A watchdog of a compute node220 in fault triggers an interrupt to the host controller 203. If afault is within the host controller 203, then the watchdog triggers areset to the board. The watchdog then remains in a latched failed stateuntil a CPU reset occurs followed by a valid service sequence.

[0179] Each processor node ASIC 234 accesses a DIAG3 signal that iswired to an HA register, and is used to strobe the compute element'shardware watchdog monitor. A DIAG2 signal is wired to the hostprocessor's embedded programmable interrupt controller (EPIC) and isused by a compute element to generate a general purpose interrupt to thehost controller 203.

[0180] A majority voter (hereinafter “voter”) is a dual softwaresub-system state machine that identifies faults within each of theprocessors (e.g., the host controller 230 and each compute node 220a-220 d) and also of the processor board 118 itself. The local voter canreset individual processors (e.g., a compute node 220) by asserting aCHECKSTOP_IN to that processor. The board level voter can force a resetof the board by asserting a master reset, wherein all processors arereset. Both voters follow a rule set that the output will follow themajority of non-checkstopped processors. If there are more processors ina fault condition than a non-fault condition, the voter will force aboard reset. Of course, other embodiments may use other rules, or canuse a single sub-system to accomplish the same purpose.

[0181] A majority voter is illustrated in FIG. 4. Board level resets areinitiated from a variety of sources. One such source is a voltagesupervisor (e.g., the power status/control device 240) which cangenerate a 200 ms reset if the voltage (e.g., VCC) rises above apredetermined threshold, such as 4.38 volts (this is also used in theillustrated embodiment in a pushbutton reset switch 406, however, thepush button can also be a separate signal). The board level voter willcontinue to drive a RESET_0 408 until both the voltage supervisor 404and the PCI_RESET_0 410 are de-asserted. Either reset will generate thesignal RESET_0 412 which resets the card into a power-on state. RESET_0412 also generates HRESET_0 414 and TRST 416 signals to each processor.Further, a HRESET_0 and TRSTcan be generated by the JTAG ports using aJTAG_HRESET_0 418 and JTAG_TRST 420 respectively. The host controller203 can generate a reset request, a soft reset (C_SRESET_0 422) to eachprocessor, a check-stop request, and an ASIC reset (CE_RESET_0 424) toeach of the four compute element's ASIC. A discrete word from the5v-powered reset PLD will generate the signal NPORESET_1 (not a power onreset). This signal is fed into the host processor discrete input word.The host processor will read this signal as logic low only if it iscoming out of reset due to either a power condition or an external resetfrom off board. Each compute element, as well as the host processor canrequest a board level reset. These requests are majority voted, and theresult RESET-VOTE_0 will generate a board level reset.

[0182] Each compute node processor 228 has a hard reset signal driven bythree sources gated together: a HRESET_0 pin 426 on each ASIC, aHRESET_0 418 from the JTAG connector 232, and a HRESET_0 412 from themajority voter. The HRESET_0 pin 426 from the ASIC is set by the “noderun” bit field (bit 0) of the ASIC Miscon_A register. Setting HRESET_0426 low causes the node processor to be held in reset. HRESET_0 426 islow immediately after system reset or power-up, the node processor isheld in reset until the HRESET_0 line is pulled high by setting the noderun bit to 1. The JTAG HRESET_0 418 is controlled by software when aJTAG debugger module is connected to the card. The HRESET_0 412 from themajority voter is generated by a majority vote from all healthy nodes toreset.

[0183] When a processor reset is asserted, the compute processor 228 isput into reset state. The compute processor 228 remains in a reset stateuntil the RUN bit 0 of the Miscon_A register is set to 1 and the hostprocessor has released the reset signals in the discrete output word.The RUN bit is set to 1 after the boot code has been loaded into theSDRAM starting at location 0x0000_(—)0100. The ASIC maps the resetvector 0xFFF0_(—)0100 generated by the MPC7400 to address0x0000_(—)0100.

[0184] Turning now to discuss memory devices 205 coupled with the hostcontroller 203, the memory devices are addressable by the hostcontroller 203 as follows. The host controller 203 addresses the memorydevices (e.g., the HA registers 212, SDRAM 214, Flash 216 and NVRAM 218)using two address mapping configurations designated as address map A andaddress map B, although other configurations are possible. Address map Aconforms to the PowerPC reference platform (PreP) specification(however, if other host controllers are used, map A conforms with anative reference platform to that host controller). Address map Bconforms to the host controller 203 common hardware reference platform(CHRP).

[0185] Support of map A is provided for backward compatibility, andfurther supports any retrofitting of existing base stationconfigurations. The address space of map B is divided into four areas:system memory, PCI memory, PCI Input/Output (I/O), and system ROM space.When configured for map B, the host controller translates addressesacross the internal peripheral logic bus and the external PCI bus asfollows: Processor Core Address Range Hex Decimal PCI Address RangeDefinition 0000_0000 0009_FFFF 0 640 K − 1 NO PCI CYCLE System memory000A_0000 000F_FFFF 640 K 1 M − 1 000A_0000-000FF_FFF Compatibility hole0010_0000 3FFF_FFFF 1 M 1 G − 1 N0 PCI CYCLE System memory 4000_00007FFF_FFFF 1 G 2 G − 1 N0 PCI CYCLE Reserved 8000_0000 FCFF_FFFF 2 G 4 G− 48 M − 1 8000_0000-FCFF_FFFF PCI memory FD00_0000 FDFF_FFFF 4 G − 48 M4 G − 32 M − 1 0000_0000-00FF_FFFF PCI/ISA memory FE00_0000 FE7F_FFFF 4G − 32 M 4 G − 24 M − 1 0000_0000-007F_FFFF PCI/ISA I/O FE80_0000FEBF_FFFF 4 G − 24 M 4 G − 20 M − 1 0080_0000-00BF_FFFF PCI I/OFEC0_0000 FEDF_FFFF 4 G − 20 M 4 G − 18 M − 1 CONFIG_ADDR PCIconfiguration address FEE0_0000 FEEF_FFFF 4 G − 18 M 4 G − 17 M − 1CONFIG_DATA PCI configuration data FEF0_0000 FEFF_FFFF 4 G − 17 M 4 G −16 M − 1 FEF0_0000-FEFF_FFFF PCI interrupt acknowledge FF00_0000FF7F_FFFF 4 G − 16 M 4 G − 8 M − 1 FF00_0000-FF7F_FFFF 32/64-bitFlash/ROM FF80_0000 FFFF_FFFF 4 G − 8 M 4 G − 1 FF80_0000-FFFF_FFFF8/32/64-bit Flash/ROM

[0186] In the illustrated embodiment, hex address FF00_(—)0000 throughFF7F_FFFF is not used, and hence, that bank of Flash ROM is not used.The address of FF80_(—)0000 through FFFF_FFFF is used, as the Flash ROMis configured in 8-bit mode and is addressed as follows: Bank SelectProcessor Core Address Range Definition 11111 FFE0_0000 FFEF_FFFFAccesses Bank 0 11110- FFE0_0000 FFEF_FFFF Application code (30 pages)00001 FFE0_0000 FFEF_FFFF Application/boot code 00000 XXXX FFF0_0000FFFF_CFFF Application/boot code FFFF_D000 FFFF_D000 Discrete input word0 FFFF_D001 FFFF_D001 Discrete input word 1 FFFF_D002 FFFF_D002 Discreteoutput word 0 FFFF_D003 FFFF_D003 Discrete output word 1 FFFF_D004FFFF_D004 Discrete output word 2 FFFF_D010 FFFF_D010 IC (Pendinginterrupt) FFFF_D011 FFFF_D011 IC (Interrupt mask low) FFFF_D012FFFF_D012 IC (Interrupt clear low) FFFF_D013 FFFF_D013 IC (Unmasked,pending low) FFFF_D014 FFFF_D014 IC (Interrupt input low) FFFF_D015FFFF_D015 Unused (read FF) FFFF_D016 FFFF_D016 Unused (read FF)FFFF_D017 FEFF_D017 Unused (read FF) FFFF_D018 FFFF_D018 Unused (readFF) FFFF_D019 FFFF_D019 Unused (read FF) FFFF_D020 FFFF_D020 HA (LocalHA register) FFFF_D021 FFFF_D021 HA (Node 0 HA register) FFFF_D022FFFF_D022 HA (Node 1 HA register) FFFF_D023 FFFF_D023 HA (Node 2 HAregister) FFFF_D024 FFFF_D024 HA (Node 3 HA register) FFFF_D025FFFF_D025 HA (8240 HA register) FFFF_D026 FFFF_D026 HA (Software Fail)FFFF_D027 FFFF_D027 HA (Watchdog Strobe) FFFF_D028 FFFF_DFFF 4068 BytesFlash FFFF_E000 FFFF_FFFF 8K NVRAM

[0187] Address FFEF_(—)0000 through FFEF_FFFF contains 30 pages, and isused for application and boot code, as selected by the Flash bank bits.Further, there a 2 Mbyte block available after reset. Data movementoccurs on the PCI 211 a and/or a memory bus.

[0188] DMA Engine Supported by Host Controller and FPGA

[0189] Direct memory access (DMA) is performed by the host controller203, and operates independently from the host processor 203 core, asillustrated in FIG. 5. The host controller 203 has an integrated DMAengine including a DMA command stack 502, a DMA state engine 504, anaddress decode block 506, and three FIFO interfaces 508, 510, 512. TheDMA engine receives and sends information via the PXB 208 coupled withthe crossbar 206.

[0190] The command stack 502 and state machine 504 processes DMArequests and transfers. The stack 502 and state machine 504 can initiateboth cycle stealing and burst mode, along with host controllerinterupts. The address decode 506 sets the bus address, and triggerstransmissions of the data.

[0191] The host controller 203 has two DMA I/O interfaces, each with a64-byte queue to facilitate the gathering and sending of data. Both thelocal processor and PCI masters can initiate a DMA transfer. The DMAcontroller supports memory transfers between PCI to memory, betweenlocal and PCI memory, and between local memory devices. Further, thehost controller 203 can transfer in either block mode or scatter modewithin discontinuous memory. A receiving channel 510 buffers data thatis to be received by the memory. A transmit channel 512 buffers datathat is sent from memory. Of course, the buffers can also send/receiveinformation from other devices, e.g., the compute nodes 220, or otherdevices capable of DMA transfers.

[0192] The host controller 203 contains an embedded programmableinterrupt controller (EPIC) device. The interrupt controller implementsthe necessary functions to provide a flexible and general-purposeinterrupt controller. Further, the interrupt controller can poolinterrupts generated from the several external components (e.g., thecompute elements), and deliver them to the processor core in aprioritized manner. In the illustrated embodiment, an OpenPICarchitecture is used, although it can be appreciated by one skilled inthe art that other such methods and techniques can be used. Here, thehost controller 203 supports up to five external interrupts, fourinternal logic-driven interrupts, and four timers with interrupts.

[0193] Data transfers can also take effect via the FPGA programinterface 508. This interface can program and/or accept data fromvarious FPGAs, e.g., the compute note ASIC 234, crossbar 242, and otherdevices. Data transfers within the compute node processor 228 to itsASIC 234 and RACEway™ bus 246 are addressed as follows: From Address ToAddress Function 0x0000 0000 0x0FFF FFFF Local SDRAM 256 Mb 0x1000 00000x1FFF FFFF crossbar 256 Mb map window 1 0x2000 0000 0x2FFF FFFFcrossbar 256 MB map window 2 0x3000 0000 0x3FFF FFFF crossbar 256 MB mapwindow 3 0x4000 0000 0x4FFF FFFF crossbar 256 MB map window 4 0x50000000 0x5FFF FFFF crossbar 256 MB map window 5 0x6000 0000 0x6FFF FFFFcrossbar 256 MB map window 6 0x7000 0000 0x7FFF EFEF crossbar 256 MB mapwindow 7 0x8000 0000 0x8FFF FFFF crossbar 256 MB map window 8 0x90000000 0x9FFF FFFF crossbar 256 MB map window 9 0xA000 0000 0xAFFF FFFFcrossbar 256 MB map window A 0xB000 0000 0xBFFF FFFF crossbar 256 MB mapwindow B 0xC000 0000 0xCFFF FFFF crossbar 256 MB map window C 0xD0000000 0xDFFF FFFF crossbar 256 MB map window D 0xE000 0000 0xEFFF FFFFcrossbar 256 MB map window E 0xF000 0000 0xFBFF FBFF Not used (CE regreplicated mapping) 0xFBFF FC00 0xFBFF FDFF Internal CN ASIC registers0xFBFF FE00 0xFEFF FFFF Pre-fetch control 0xFF00 0000 0xFFFF FFFF 16 MBboot FLASH memory area

[0194] Thc SDRAM 236 can be addressable in 8, 16, 32 or 64 bitaddresses. The RACEway™ bus 246 supports locked read/write and lockedread transactions for all data sizes. A 16 Mbyte boot flash area isfurther divided as follows: From Address To Address Function 0xFF00 20060xFF00 2006 Software Fail Register 0xFF00 2005 0xFF00 2005 MPC8240 HARegister 0xFF00 2004 0xFF00 2004 Node 3 HA Register 0xFF00 2003 0xFF002003 Node 2 HA Register 0xFF00 2002 0xFF00 2002 Node 1 HA Rcgister0xFF00 2001 0xFF00 2001 Node 0 HA Register 0xFF00 2000 0xFF00 2000 LocalHA Register (status/control) 0xFF00 0000 0xFF00 1FFF NVRAM

[0195] Slave accesses are accesses initiated by an external RACEway™device directed toward the compute element processor 238. The ASIC 234supports a 256 Mbyte address space which can be partitioned as follows:From Address To Address Function 0x0000 0000 0x0FFF FBFF 256 MB less 1Kb hole SDRAM 0Xfff_FC00 0xFFF_FFFF PCE 133 internal registers

[0196] There are 16 discrete output signals directly controllable andreadable by the host controller 203. The 16 discrete output signals aredivided into two addressable 8-bit words. Writing to a discrete outputregister will cause the upper 8-bits of the data bus to be written tothe discrete output latch. Reading a discrete output register will drivethe 8-bit discrete output onto the upper 8-bits of the host processordata bus. The bits in the discrete output word are defined as follows:

[0197] There are 16 discrete input signals accessible by the hostcontroller 203. Reads from the discrete input address space will latchthe state of the signals, and return the latched state of the discreteinput signals to the host processor. The bits in the discrete input wordare as follows: DH(0:7) Signal Description Output Word 2 0ND0_FLASH_EN_1 Enable the CE ASIC's FLASH port when 1 1 ND1_FLASH_EN_1Enable the CE ASIC's FLASH port when 1 2 ND2_FLASH_EN_1 Enable the CEASIC's FLASH port when 1 3 ND3_FLASH_EN_1 Enable the CE ASIC's FLASHport when 1 4 Wrap 1 Wrap to discrete input 5 6 7 Output Word 1 0 WRAP0Wrap to Discrete Input 1 I2C_RESET_0 Reset the 12C serial bus when 0 2SWLED Software controlled LED 3 FLASHSEL4 Flash bank select address bit4 4 FLASHSEL3 Flash bank select address bit 3 5 FLASHSEL2 Flash bankselect address bit 2 6 FLASHSEL1 Flash bank select address bit 1 7FLASHSEL0 Flash bank select address bit 0 Output Word 0 0 C_SRESET3_0Issue a Soft Reset to CPU on Node 3 when 0 1 C_PRESET3_0 Reset PCE133ASIC Node 3 when 0 2 C_SRESET2_0 Issue a Soft Reset to cpu on Node 2when 0 3 C_PRESET2_0 Reset PCE133 ASIC Node 2 when 0 4 C_SRESET1_0 Issuea Soft Reset to cpu on Node 1 when 0 5 C_PRESET1_0 Reset PCE133 ASICNode 1 when 0 6 C_SRESET0_0 Issue a Soft Reset to cpu on Node 0 when 0 7C_PRESET0_0 Reset PCE133 ASIC Node 0 when 0 Input Word 1 0 WRAP 1 Wrapfrom discrete output word 1 2 V3.3_FAIL_0 Latched status of power supplysince last reset 3 V2.5_FAIL_0 Latched status of power supply since lastreset 4 VCORE1_FAIL_0 Latched status of power supply since last reset 5VCORE0_FAIL_0 Latched status of power supply since last reset 6RIOR_CNF_DONE_1 RIO/RACE++ FPGA configuration complete 7 PXB0_CNF_DONE_1PXB++ FPGA configuration complete Input Word 0 0 WRAP0 Wrap fromdiscrete output word 1 WDMSTATUS MPC8240's watchdog monitor status (0 =failed) 2 NPORESET_1 Not a power on reset when high 3 4 5 6 7

[0198] The host controller 203 interfaces with an 8-input interruptcontroller external from processor itself (although in other embodimentsit can be contained within the processor). The interrupt inputs arewired, through the controller to interrupt zero of the host processorexternal interrupt inputs. The remaining four host processor interruptinputs are unused.

[0199] The Interrupt Controller comprises the following five 8-bitregisters: Resister Description Pending Register A low bit indicatcs afalling edge was detected on that interrupt (read only); Clear RegisterSetting a bit low will clear the corresponding latched interrupt (writeonly); Mask Register Setting a bit low will mask the pending interruptfrom generating a processor interrupt; Unmasked Pending A low bitindicates a pending interrupt that is not Register masked out InterruptState indicates the actual logic level of each Register interrupt inputpin.

[0200] The interrupt input sources and their bit positions within eachof the six registers are as follows: Bit Signal Description 0 SWFAIL_08240 Software Controlled Fail Discrete 1 RTC_INT_0 Real time clock event2 NODE0_FAIL_0 WDFAIL_0 or IWDFAIL_0 or SWFAIL_0 active 3 NODE1_FAIL_0WDFAIL_0 or IWDFAIL_0 or SWFAIL_0 active 4 NODE2_FAIL_0 WDFAIL_0 orIWDFAIL_0 or SWFAIL_0 active 5 NODE3_FAIL_0 WDFAIL_0 or IWDFAIL_0 orSWFAIL_0 active 6 PCI_INT_0 PCI interrupt 7 XB_SYS_ERR_0 crossbarinternal error

[0201] A falling edge on an interrupt input will set the appropriate bitin the pending register low. The pending register is gated with the maskregister and any unmasked pending interrupts will activate the interruptoutput signal to the host processor external interrupt input pin.Software will then read the unmasked pending register to determine whichinterrupt(s) caused the exception. Software can then clear theinterrupt(s) by writing a zero to the corresponding bit in the clearregister. If multiple interrupts are pending, the software has theoption of either servicing all pending interrupts at once and thenclearing the pending register or servicing the highest priorityinterrupt (software priority scheme) and the clearing that singleinterrupt. If more interrupts are still latched, the interruptcontroller will generate a second interrupt to the host processor forsoftware to service. This will continue until all interrupts have beenserviced.

[0202] An interrupt that is masked will show up in the pending registerbut not in the unmasked pending register and will not generate aprocessor interrupt. If the mask is then cleared, that pending interruptwill flow through the unmasked pending register and generate a processorinterrupt.

[0203] The multiple components within the processor board 118 dictatevarious power requirements. The processor board 118 requires 3.3V, 2.5V,and 1.8V. In the illustrated embodiment, there are two processor corevoltage supplies 302, 304 each driving two 1.8V cores for two processors(e.g., 228). There is also a 3.3V supply 306 and a 2.5V supply 308 whichsupply voltage to the remaining components (e.g., crossbar 206,interface block 205 and so on). To provide power to the board, the threevoltages (e.g., the 1.8V, 3.3V and 2.5V) have separate switchingsupplies, and proper power sequencing. All three voltages are convertedfrom 5.0V. The power to the processor card 118 is provided directly fromthe modem board 112 within the base station, however, in otherembodiments there is a separate or otherwise integrated power supply.The power supply a preferred embodiment is rated as 12A, however, inother embodiments the rating varies according to the specific componentrequirements.

[0204] In the illustrated embodiment, for instance, the 3.3V powersupply 306 is used to provide power to the NVRAM 218 core, SDRAM 214,PXB 208, and crossbar ASIC 206 (or FPGA is present). This power supplyis rated as a function of the devices chosen for these functions.

[0205] A 2.5V power supply 308 is used to provide power to the computenode ASIC 234 and can also power the PXB 208 FPGA core. The hostprocessor bus can run at 2.5V signaling. The host bus can operate at2.5V signaling.

[0206] The power-on sequencing is necessary in multi-voltage digitalboards. One skilled in the art can appreciate that power sequencing isnecessary for long-term reliability. The right power supply sequencingcan be accomplished by using inhibit signals. To provide fail-safeoperation of the device, power should be supplied so that if the coresupply fails during operation, the I/O supply is shut down as well.

[0207] Although in theory, the general rule is to ramp all powersupplies up and down at the same time as illustrated in FIG. 6. The rampup 602 and ramp down 604 show agreement with the power supplies 302,304, 306, 308 over time. One skilled in the art realizes that inreality, voltage increases and decreases do not occur among multiplepower supplies in such a simultaneous fashion.

[0208]FIG. 7 shown the actual voltage characteristics for theillustrated embodiment. As can be seen, ramp up 702 a-702 c and rampdown 704 a-704 c sequences depend on multiple factors, e.g., powersupply, total board capacities that need to be charged, power supplyload, and so on. For example, the ramp up for the 3.3V supply 702 aoccurs before the ramp up for the 2.5V supply 702 c, which occurs beforethe ramp up of the 1.8V supplies 702 b. Further, the ramp down for the3.3V supply 704 a occurs before the ramp down for the 2.5V supply 704 c,which occurs before the ramp down for the 1.8V supplies 704 c.

[0209] Also, The host processor requires the core supply to not exceedthe I/O supply by more than 0.4 volts at all times. Also, the I/O supplymust not exceed the core supply by more than 2 volts. Therefore, toachieve an acceptable power-up and power-down sequencing, e.g., to avoiddamage to the components, a circuit containing diodes is used inconjunction with the power supplied within the base station.

[0210] The power status/control device 240 is designed from aprogrammable logic device (PLD). The PLD is used to monitor the voltagestatus signals from the on board supplies. It is powered up from +5V andmonitors +3.3V, +2.5V, 1.8V_(—)1 and +1.8V_(—)2. This device monitorsthe power_good signals from each supply. In the case of a power failurein one or more supplies, the PLD will issue a restart to all suppliesand a board level reset to the processor board. A latched power statussignal will be available from each supply as part of the discrete inputword. The latched discrete can indicate any power fault condition sincethe last off-board reset condition.

[0211] In operation, the processor board inputs raw antenna data fromthe base station modem card 112 (or other available location of thatdata), detects sources of interference within that data, and produces anew stream of data which has reduced interference subsequentlytransmitting that refined data back to the modem card (or otherlocation) for further processing within the base station.

[0212] As can be appreciated by one skilled in the art, suchinterference reduction is computationally complex; hence, the hardwaremust support throughputs sufficient for multiple user processing. In apreferred embodiment, characteristics of processing are a latency ofless than 300 microseconds handing data in the 110 Mbytes/Sec range,however, in other embodiments the latency and data load can vary.

[0213] In the illustrated embodiment, data from the modem board issupplied via the PCI bus 211 b through the PCI bridge 222. From there,the data traverses the crossbar 206 and is loaded into the hostcontroller memory 205. Output data flows in the opposite direction.Additionally, certain data flows between the host controller 203 and thecompute elements 220.

[0214] Hybrid Operating System

[0215] The compute elements 220 operate, in some embodiments, under theMC/OS operating system available commercially from the assignee herein,although different configurations can run under different operatingsystems suited for such. Here, one aspect is to reduce the use ofnon-POSIX system calls which can increase portability of the multipleuser detection software among different hardware environments andoperating system environments. The host processor is operated by theVxWorks operating system, as is required by MC/OS and suitable for aMotorola 8240 PowerPC.

[0216]FIG. 8 shows a block diagram of various components within thehardware/software environment. An MC/OS subsystem 802 is used as anoperating system for the compute elements 220. Further, a MC/OS DX 804provides APIs acceptable overhead and latency access to the DMA engineswhich in turn provide suitable bandwidth transfers of data. DX 804 canbe used to move data between the compute elements 220 during parallelprocessing, and also to move data between the compute elements 220, thehost controller 203, and the modem card 112. As described above, eachcompute element 220 continues an application 806, and a watchdog 808.Further, the HA registers provide the bootstrap 810 necessary forstart-up.

[0217] The host controller 203 runs under the VxWorks operating system812. The host processor 202 contains a watchdog 814, application data816, and a bootstrap 818. Further, the host processor 202 can performTCP/IP stack processing 820 for communication through the Ethernetinterface 224.

[0218] Input/output between the processor card 118 and the modem card112 takes place by moving data between the Race++ Fabric and the PCI bus211 b via the PCI bridge 222. The application 806 will use DX toinitialize the PXB++ bridge, and to cause input/output data to move asif it were regular DX IPC traffic. For example, there are severalcomponents which can initiate data transfers and choose PCI addresses tobe involved with the transfers.

[0219] One approach to increasing available on the processor card 118 isto balance host-processing time against application execution. Forexample, when the system comes up, the application determines whichprocessing resources are available, and the application determines aload mapping on the available resources and record certain parameters inNVRAM. Although briefs interruptions in service can occur, theapplication does not need to know how to continue execution acrossfaults. For instance, the application can make an assumption that thehardware configuration will not change without the system firstrebooting. If the application is in a state which needs to be preservedacross reboots, the application checkpoints the data on a regular basis.The system software provides an API to a portion of the NVRAM for thispurpose

[0220] The host controller 203 is attached to an amount of linear flashmemory 216 as discussed above. This flash memory 216 serves severalpurposes. The first purpose the flash memory serves is as a source ofinstructions to execute when the host controller comes out of reset.Linear flash can be addressed much like normal RAM. Flash memories canbe organized to look like disk controllers; however in thatconfiguration they generally require a disk driver to provide access tothe flash memory. Although such an organization has several benefitssuch as automatic reallocation of bad flash cells, and write wearleveling, it is not appropriate for initial bootstrap. The flash memory216 also serves as a file system for the host and as a place to storepermanent board information (e.g., such as a serial number).

[0221] When the host controller 203 first comes out of reset, memory isnot turned on. Since high-level languages such as C assume some memoryis present (e.g., for a stack) the initial bootstrap code must be codedin assembler. This assembler bootstrap contains a few hundred lines ofcode, sufficient to configure the memory controller, initialize memory,and initialize the configuration of the host processor internalregisters.

[0222] After the assembler bootstrap has finished execution, control ispassed to the processor HA code (which is also contained in boot flashmemory). The purpose of the HA code is to attempt to configure thefabric, and load the compute element CPUs with HA code. Once this iscomplete, all the processors participate in the HA algorithm. The outputof the algorithm is a configuration table which details which hardwareis operational and which hardware is not. This is an input to the nextstage of bootstrap, the multi-computer configuration.

[0223] MC/OS expects the host controller system to configure themulti-computer (e.g., compute elements 220). A configmc program reads atextual description of the computer system configuration, and produces aseries of binary data structures that describe the system configuration.These data structures are used in MC/OS to describe the routing andconfiguration of the multi-computer.

[0224] The processor board 118 will use almost exactly the same sequenceto configure the multi-computer. The major difference is that MC/OSexpects configurations to be static, whereas the processor boardconfiguration changes dynamically as faulty hardware cause variousresources to be unavailable for use.

[0225] One embodiment of the invention uses binary data structuresproduced by configmc to modify flags that indicate whether a piece ofhardware is usable. A modification to MC/OS prevents it from usinghardware marked as broken. Another embodiment utilizes the output of theHA algorithm to produce a new configuration file input to configmc, theconfigmc execution is repeated with the new file, and MC/OS isconfigured and loaded with no knowledge of the broken hardwarewhatsoever. This embodiment can calculate an optimal routing table inthe face of failed hardware, increasing the performance of the remainingoperational components.

[0226] After the host controller has configured the compute elements220, the runmc program loads the functional compute elements with a copyof MC/OS. Because access to the processor board 118 from a TCP/IPnetwork is required, the host computer system acts as a connection tothe TCP/IP network. The VxWorks operating system contains a fullyfunctional TCP/IP stack. When compute elements access network resources,the host computer acts as proxy, exchanging information with the computeelement utilizing DX transfers, and then making the appropriate TCP/IPcalls on behalf of the compute element.

[0227] The host controller 203 needs a file system to storeconfiguration files, executable programs, and MC/OS images. For thispurpose, flash memory is utilized. Rather than have a separate flashmemory from the host controller boot flash, the same flash is utilizedfor both bootstrap purposes and for holding file system data. The flashfile system provides DOS file system semantics as well as write wearleveling.

[0228] There are in particular, two portions of code which can beremotely updated; the bootstrap code which is executed by the hostcontroller 203 when it comes out of reset, and the rest of the codewhich resides on the flash file system as files.

[0229] When code is initially downloaded to the processor board 118, itis written as a group of files within a directory in the flash filesystem. A single top-level index tracks which directory tree is used forbooting the system. This index continues to point at the existingdirectory tree until a download of new software is successfullycompleted. When a download has been completed and verified, thetop-level index is updated to point to the new directory tree, the bootflash is rewritten, and the system can be rebooted.

[0230] Fault detection and reporting 820, 822 is performed by havingeach CPU in the system gather as much information about what it observedduring a fault, and then comparing the information in order to detectwhich components could be the common cause of the symptoms. In somecases, it may take multiple faults before the algorithm can detect whichcomponent is at fault.

[0231] Failures within the processor board 118 can be a single pointfailure. Specifically, everything on the board is a single point offailure except for the compute elements. This means that the only hardfailures that can be configured out are failures in the compute elements220. However, many failures are transient or soft, and these can berecovered from with a reboot cycle.

[0232] In the case of hard failure of a compute element 220, theapplication executes with reduced demand for computing resources. Forexample, the application may work with a smaller number of interferencesources, or perform interference cancellation iterations, but stillwithin a tolerance.

[0233] Failure of more than a single compute element will cause theboard to be inoperative. Therefore, the application only needs to handletwo configurations: all compute elements functional and 1 computeelement unavailable. Note that the single crossbar means that there areno issues as to which processes need to go on which processors—thebandwidth and latencies for any node to any other node are identical onthe processor board, although others methods and techniques can be used.

[0234] DSP Connected to Processing Board

[0235]FIG. 9 shows an embodiment of the invention wherein a digitalsignal processor (DSP) 900 is connected with the processor board 118.Such configuration enables a DSP to communicate via DMA with processorboard. One skilled in the art can appreciate that DMA transfers can befaster than bus transfers, and hence, throughput can be increased.Shown, is a DSP processor, a buffer, a FPGA and a crossbar.

[0236] The DSP 900 generates a digital signal corresponding to an analoginput, e.g., a rake receiver. The DSP 900 operates in real-time, hence,the output is clocked to perform transfers of the digital output. In theillustrated embodiment, the DSP can be a Texas Instruments modelTMS320C67XX series, however, other DSP processors are commerciallyavailable which can satisfy the methods and systems herein.

[0237] A buffer 902 is coupled with the DSP 900, and receives and senddata in a First-In First-Out (e.g., queue) fashion, also referred to asa FIFO buffer. The buffer 902, in some embodiments, can be dual-portedRAM of sufficient size to capture data transfers. One skilled in the artcan appreciate, however, that a protocol can be utilized to transfer thedata where the buffer or dual-ported RAM is smaller that the datatransfer size.

[0238] A FPGA 904 is coupled with both the buffer 902 and an crossbar906 (which can be the same crossbar coupled with the compute elements220 and host controller 203). The FPGA 904 moves data from the buffer902 to the crossbar 906, which subsequently communicates the data tofurther devices, e.g., a RACEway™ or the host controller 203 or computeelements 220. The FPGA 904 also perform data transfers directly from theDSP 900 to the crossbar 906. This method is utilized in some embodimentswhere data transfer sizes can be accommodated without buffering, forinstance, although either the buffer or direct transfers can be used.

[0239] The DSP 900 contains at least one external memory interface(EMIF) 908 device, which is connected to the buffer 902 or dual-portedRAM. RACEway™ transfers actually access the RAM, and then additionalprocessing takes place within the DSP to move the data to the correctlocation in SDRAM within the DSP. In embodiments where the RAM issmaller that the data transfer size, then there is a massaging protocolbetween two endpoint DSPs exchanging messages, since the message will befragmented to be contained within the buffer or RAM.

[0240] As more RACEway™ endpoints are added (for instance, to increasespeed or throughput), the size of the dual-port RAM can be increased toa size of 2*F*N*P buffers of size F, where F is the fragment size, N isthe number of RACEway™ endpoints in communication with the DSP, and P isthe number of parallel transfers which can be active on an endpoint. Theconstant 2 represents double buffering so one buffer can be transferredto the RACEway™ simultaneously with a buffer being transferred to theDSP. One skilled in the art can appreciate that the constant can be fourtimes rather than two times to emulate a full-duplex connection. With a4 mode system, this could be, for example, 4*8K*4*4 or 512 Kbytes, plusa overhead factor for configuration and data tracking.

[0241] The FPGA 904 can program the DMA controller 910 within the DSP900 to move data between the buffer 902 and the DSP/SDRAM 912 directlyfrom a DSP host port 914. The host port 914 is a peripheral like theEMIF 908, but can master transfers into the DSP data-paths, e.g., it canread and write any location within the DSP. Hence, the host port 914 canaccess the DMA controller, 910 and can be used to initiate transfers viathe DMA engine. One skilled in the art can appreciate that using thisarchitecture, RACEway™ transfers can be initiated without thecooperation of the DSP, the thus, the DSP is free to continue processingwhile transfers take place and further, there is no need for protocolmessaging within the buffer.

[0242] The FPGA 904 can also perform fragmentation of data. Inembodiments where the buffer device is a dual-port RAM, the FPGA 904 anprogram the DMA controller within the DSP to move fragments into orout-of the DSP. This method can be used to match throughput of theexternal transfer bus, e.g., the RACEway™.

[0243] An example of the methods and systems described for a DSP, is asfollows. In an embodiment where the RACEway™ reads date out of the DSPmemory 912, this example assumes that another DSP is reading the SDRAMof the local DSP. The FPGA 904 detects a RACEway™ data packet arriving,and decodes the packet to determine that is contains instructions for adata-read at, for example, memory location 0x10000. The FPGA 904 writesover the host port interface 914 to program the DMA controller 910 totransfer data starting at memory location 0x10000, which refers to alocation in the primary EMIF 908 corresponding to a location in theSDRAM 912, and to move that data to a location in the secondary EMIF(e.g., the buffer device) 902. As data arrives in the buffer 902, theFPGA 904 reads the data out of the buffer, and moves it onto theRACEway™ bus. When a predetermined block of data is moved, the DMAcontroller 910 finishes the transfer, and the FPGA 904 finishes movingthe data from the buffer 902 to the RACEway™.

[0244] Another example assumes that another DSP is requesting a writeinstruction to the local DSP. Here, the FPGA 904 detects a data packetarriving, and determines that is it a write to location 0x20000, forinstance. The FPGA 904 fills some amount of the buffer 902 with the datafrom the RACEway™ bus, and then writes over the host port 914 interfaceto program the DMA controller 910. The DMA controller 910 then transfersdata from the buffer device 902 and writes that data to the primary EMIF908 at address 0x20000. At the conclusion of the transfer, an interruptcan be sent to the DSP 900 to indicate that a data packet has arrived,or a polling of a location in the SDRAM 912 can accomplish the samerequirement.

[0245] These two examples are non-limiting example, and otherembodiments can utilize different methods and devices for the transferof data between devices. For example, if the DSP 900 utilizes RapidIOinterfaces, the buffer 902 and FPGA 904 can be modified to accommodatethis protocol. Also, the crossbar 906 illustrated may be in common witha separate bus structure, or be in common with the processor board 118described above. Even further, in some embodiments, the FPGA 904 can bedirectly coupled with the board processor, or be configured as a computenode 220.

[0246] Therefore, as can be understood by one skilled in the art, themethods and systems herein are suited for multiple user detection withinbase stations, and can be used to accommodate both short-code andlong-code receivers.

[0247] Short-Code Processing

[0248] In one embodiment of the invention using short-code receivers, apossible mapping of matrices necessary for short-code mapping is nowdiscussed. In order to perform MUD at the symbol rate, the correlationbetween the user channel-corrupted signature waveforms must becalculated. These correlations are stored as elements in matrices, herereferred to as R-matrices. Because the channel is continually changing,the correlations need be updated in real-time.

[0249] The implementation of MUD at the symbol rate can be divided intotwo functions. The first function is the calculation of the R-matrixelements. The second function is interference cancellation, which relieson knowledge of the R-matrix elements. The calculation of these elementsand the computational complexity are described in the following section.Computational complexity is expressed in Giga-Operations Per Second(GOPS). The subsequent section describes the MUD IC function. The methodof interference cancellation employed is Multi-stage Decision FeedbackIC (MDFIC).

[0250] The R-matrix calculations can be divided into three separatecalculations, each with an associated time constant for real-timeoperation, as follows: $\begin{matrix}{{r_{lk}\left\lbrack m^{\prime} \right\rbrack} = {\sum\limits_{q = 1}^{L}{\sum\limits_{q^{\prime} = 1}^{L}{{Re}\left\lbrack {{\hat{a}}_{lq}^{*}{a_{kq} \cdot \frac{1}{2N_{l}}}{\sum\limits_{n}{\sum\limits_{p}{g\left\lbrack {{\left( {n - p} \right)N_{c}} +} \right.}}}} \right.}}}} \\{{\left. {{m^{\prime}T} + \tau_{lq} - \tau_{{lq}^{\prime}}} \right\rbrack}{{c_{k}\lbrack p\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}} \\{= {{r_{lk}\left\lbrack m^{\prime} \right\rbrack} = {\sum\limits_{q = 1}^{L}{\sum\limits_{q^{\prime} = 1}^{L}{{Re}\left\lbrack {a_{lq}^{*}{a_{kq} \cdot {c_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack}}} \right\rbrack}}}}} \\{{C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{\sum\limits_{p}{{g\left\lbrack {{\left( {n - p} \right)N_{c}} + {m^{\prime}T} + \tau_{lq} - \tau_{{lq}^{\prime}}} \right\rbrack}{{c_{k}\lbrack p\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}}}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}{\sum\limits_{p}{g\left\lbrack {{mN}_{c} + {m^{\prime}T} + \tau_{lq} - \tau_{{lq}^{\prime}}} \right\rbrack}}}}} \\{{\sum\limits_{n}{{c_{k}\left\lbrack {n - m} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}{\sum\limits_{p}{{g\left\lbrack {{mN}_{c} + {m^{\prime}T} + \tau_{lq} - \tau_{{lq}^{\prime}}} \right\rbrack}{\Gamma_{lk}\lbrack m\rbrack}}}}}} \\{{\Gamma_{lk}\lbrack m\rbrack} = {\sum\limits_{n}{{c_{k}\left\lbrack {n - m} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}\end{matrix}$

[0251] Where the hats are omitted otherwise indicating parameterestimates. Hence we must calculate the R-matrices, which depend on theC-matrices, which in turn, depend on the Γ-matrix. The Γ-matrix has theslowest time constant. This matrix represents the user code correlationsfor all values of offset In. For a case of 100 voice users the totalmemory requirement is 21 MBytes based on two bytes (real and imaginaryparts) per element. This matrix is updated only when new codes (e.g.,new users) are added to the system. Hence this is essentially a staticmatrix. The computational requirements are negligible.

[0252] The most efficient method of calculation depends on the non-zerolength of the codes. For high data-rate users the non-zero length of thecodes is only 4-chips long. For these codes, a direct convolution is themost efficient method to calculation the elements. For low data-rateusers it is more efficient to calculation the elements using the FFT toperform the convolutions in the frequency domain. Further, as can beappreciated by one skilled in the art, cache memory can be used wherethe matrix is somewhat static compared with the update of othermatrices.

[0253] The C-matrix is calculated from the Γ-matrix. These elements mustbe calculated whenever a user's delay lag changes. For now, assume thaton average each multi-path component changes every 400 ms. The length ofthe g[ ] function is 48 samples. Since we are over sampling by 4, thereare 12 multiply-accumulations (real×complex) to be performed perelement, or 48 operations per element. When there are 100 low-rate userson the system (i.e., 200 virtual users) and a single multi path lag (of4) changes for one user a total of (1.5)(2)KvLNv elements must becalculated. The factor of 1.5 comes from the 3 C-matrices (m′=−1, 0, 1),reduced by a factor of 2 due to a conjugate symmetry condition. Thefactor of 2 results because both rows and columns must be updated. Thefactor Nv is the number of virtual users per physical user, which forthe lowest rate users is Nv=2. In total then this amounts to 230,400operations per multi-path component per physical user. Assuming 100physical users with 4 multi-path components per user, each changing onceper 400 ms gives 230 MOPS.

[0254] The R-matrices are calculated from the C-matrices. From theequation above the R-matrix elements are${r_{lk}\left\lbrack m^{\prime} \right\rbrack} = {{\sum\limits_{q = 1}^{L}{\sum\limits_{q^{\prime} = 1}^{L}{{Re}\left\lbrack {a_{lq}^{*}{a_{{kq}^{\prime}} \cdot {C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack}}} \right\rbrack}}} = {{Re}\left\lbrack {a_{l}^{H} \cdot {C_{lk}\left\lbrack m^{\prime} \right\rbrack} \cdot a_{k}} \right\rbrack}}$

[0255] where a_(k) are L×1 vectors, and C_(lk)[m′] are L×L matrices. Therate at which these calculations must be performed depends on thevelocity of the users. The selected update rate is 1.33 ms. If theupdate rate is too slow such that the estimated R-matrix values deviatesignificantly from the actual R-matrix values then there is adegradation in the MUD efficiency.

[0256] From the above equation the calculation of the R-matrix elementscan be calculated in terms of an X-matrix which representsamplitude-amplitude multiplies: $\begin{matrix}\left. {{r_{lk}\left\lbrack m^{\prime} \right\rbrack} = {{Re}\left\lbrack {{tr}\left\lbrack {a_{l}^{H} \cdot {C_{lk}\left\lbrack m^{\prime} \right\rbrack} \cdot a_{k}} \right.} \right\rbrack}} \right\rbrack \\{= {{Re}\left\lbrack {{tr}\left\lbrack {{C_{lk}\left\lbrack m^{\prime} \right\rbrack} \cdot a_{k} \cdot a_{l}^{H}} \right\rbrack} \right\rbrack}} \\{= {{Re}\left\lbrack {{tr}\left\lbrack {{C_{lk}\left\lbrack m^{\prime} \right\rbrack} \cdot X_{lk}} \right\rbrack} \right\rbrack}} \\{= {{{tr}\left\lbrack {{C_{lk}^{R}\left\lbrack m^{\prime} \right\rbrack} \cdot X_{lk}^{R}} \right\rbrack} - {{tr}\left\lbrack {C_{lk}^{l} \cdot X_{lk}^{l}} \right\rbrack}}}\end{matrix}$ X_(lk) ≡ a_(k) ⋅ a_(l)^(H) ≡ X_(lk)^(R) + jX_(lk)^(l)C_(lk)[m^(′)] ≡ C_(lk)^(R)[m^(′)] + jC_(lk)^(l)[m^(′)]

[0257] The X-matrix multiplies can be reused for all virtual usersassociated with a physical user and for all m′ (i.e. m′=0, 1). Hencethese calculations are negligible when amortized. The remainingcalculations can be expressed as a single real dot product of length 2L2=32. The calculations are performed in 16-bit fixed-point math. Thetotal operations is thus 1.5(4)(KvL)2=3.84 Mops. The processingrequirement is then 2.90 GOPS. The X-matrix multiplies when amortizedamount to an additional 0.7 GOPS. The total processing requirement isthen 3.60 GOPS.

[0258] From the equation above the matched-filter outputs are given by:$\begin{matrix}{{y_{l}\lbrack m\rbrack} = {{{r_{ll}\lbrack 0\rbrack}{b_{l}\lbrack m\rbrack}} + {\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\left\lbrack {- 1} \right\rbrack}{b_{k}\left\lbrack {m + 1} \right\rbrack}}} +}} \\{{{\sum\limits_{k = 1}^{K_{v}}{\left\lbrack {{r_{lk}\lbrack 0\rbrack} - {{r_{ll}\lbrack 0\rbrack}\delta_{lk}}} \right\rbrack {b_{k}\lbrack m\rbrack}}} +}} \\{{{\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\lbrack 1\rbrack}{b_{k}\left\lbrack {m - 1} \right\rbrack}}} + {\eta_{l}\lbrack m\rbrack}}}\end{matrix}$

[0259] The first term represents the signal of interest. All theremaining terms represent Multiple Access Interference (MAI) and noise.The multiple-stage decision-feedback interference cancellation (MDFIC)algorithm iteratively solves for the symbol estimates using${{\hat{b}}_{l}\lbrack m\rbrack} = {{sign}\left\{ {{y_{l}\lbrack m\rbrack} - {\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\left\lbrack {- 1} \right\rbrack}{{\hat{b}}_{k}\left\lbrack {m + 1} \right\rbrack}}} - {\sum\limits_{k = 1}^{K_{v}}{\left\lbrack {{r_{lk}\lbrack 0\rbrack} - {{r_{ll}\lbrack 0\rbrack}\delta_{lk}}} \right\rbrack {{\hat{b}}_{k}\lbrack m\rbrack}}} - {\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\lbrack 1\rbrack}{{\hat{b}}_{k}\left\lbrack {m - 1} \right\rbrack}}}} \right\}}$

[0260] with initial estimates given by hard decisions on thematched-filter detection statistics, {circumflex over(b)}₁[m]=sign{y_(l)[m]}. The MDFIC technique is closely related to theSIC and PIC technique. Notice that new estimates are immediatelyintroduced back into the interference cancellation as they arecalculated. Hence at any given cancellation step the best availablesymbol estimates are used. This idea is analogous to the Gauss-Siedelmethod for solving diagonally dominant linear systems.

[0261] The above iteration is performed on a block of 20 symbols, forall users. The 20-symbol block size represents two WCDMA time slots. TheR-matrices are assumed to be constant over this period. Performance isimproved under high input BER if the sign detector in is replaced by thehyperbolic tangent detector. This detector has a single slope parameterwhich is variable from iteration to iteration. Similarly, performance isimproved if only a fraction of the total estimated interference iscancelled (e.g., partial interference cancellation), owing to channeland symbol estimation errors.

[0262] Multiple Processors Generating Complementary R-Matrices

[0263] The three R-matrices (R[−1], R[0] and R[1]) are each Kv×Kv insize. The total number of operation then is 6K_(v) ² per iteration. Thecomputational complexity of the multistage MDFIC algorithm depends onthe total number of virtual users, which depends on the mix of users atthe various spreading factors. For Kv=200 users (e.g. 100 low-rateusers) this amounts to 240,000 operations. In the current implementationtwo iterations are used, requiring a total of 480,000 operations. Forreal-time operation these operations must be performed in {fraction(1/15)} ms. The total processing requirement is then 7.2 GOPS.Computational complexity is markedly reduced if a threshold parameter isset such that IC is performed only for values |y_(l)[m]| below thethreshold. The idea is that if |y_(l)[m]| is large there is little doubtas to the sign of b_(l)[m], and IC need not be performed. The value ofthe threshold parameter is variable from stage to stage.

[0264] Although three R matrices are output from the R matrixcalculation function, only half of the elements are explicitlycalculated. This is because of symmetry that exists between R matrices:

R _(l,k) =ξR _(k,l)(−m)

[0265] Therefore, only two matrices need to be calculated. The first oneis a combination of R(1) and R(−1). The second is the R(0) matrix. Inthis case, the essential R(0) matrix elements have a triangularstructure to them. The number of computations performed to generate theraw data for the R(1)/R(−1) and R(0) matrices are combined and optimizedas a single number. This is due to the reuse of the X-matrix outerproduct values across the two R-matrices. Since the bulk of thecomputations involve combining the X-matrix and correlation values, theydominate the processor utilization. These computations are used as acost metric in determining the optimum loading of each processor.

[0266] Processor Loading Optimization

[0267] The optimization problem is formulated as an equal area problem,where the solution results in each partition area to be equal. Since themajor dimensions of the R-matrices are in terms of the number of activevirtual users, the solution space for this problem is in terms of thenumber of virtual users per processor. By normalizing the solution spaceby the number of virtual users, the solution is applicable for anarbitrary number of virtual users.

[0268]FIG. 10 shows a model of the normalized optimization scenario. Thecomputations for the R(1)/R(−1) matrix are represented by the squareHJKM, while the computations for the R(0)matrix are represented by thetriangle ABC. From geometry, the area of a rectangle of length b andheight h is:

A_(r)=bh

[0269] For a triangle with a base width b and height h , the area iscalculated by: $A_{t} = {\frac{1}{2}b\quad h}$

[0270] When combined with a common height a, the formula for the areabecomes: $\begin{matrix}{A_{i} = {A_{r\quad i} + A_{t\quad i}}} \\{= {{a_{i}a_{e}} + {\frac{1}{2}a_{i}^{2}}}}\end{matrix}$

[0271] The formula for A gives the area for the total region below thepartition line. For example, the formula for A2 gives the area withinthe rectangle HQRM plus the region within triangle AFG. For the costfunction, the difference in successive areas is used. That is:$\begin{matrix}{B_{i} = {A_{i} - A_{i - 1}}} \\{= {{\frac{1}{2}a_{i}^{2}} + a_{i} - {\frac{1}{2}a_{i - 1}^{2}} - a_{i - 1}}}\end{matrix}$

[0272] For an optimum solution, the B must be equal for i=1,2, . . . ,N,where N is the number of processors performing the calculations. Becausethe total normalized load is equal to AN, the loading per processor loadis equal to AN/N,${B_{i} = {\frac{A_{N}}{N} = {\frac{A_{3}}{3} = \frac{3}{2\quad N}}}},{{\text{for}\quad i} = 1},{2\quad \ldots}\quad,{N.}$

[0273] By combining the two equations for B, the solution for a_(i) isfound by finding the roots of the equation:${{\frac{1}{2}a_{i}^{2}} + a_{i} - {\frac{1}{2}a_{i - 1}^{2}} - a_{i - 1} - \frac{3}{2N}} = 0$

[0274] The solution for a is:${a_{i} = {{- 1} \pm \sqrt{1 + a_{{- 1}i}^{2} + {2a_{i - 1}} + \frac{3}{N}}}},{{\text{for}\quad i} - 1},2,\ldots \quad,N$

[0275] Since the solution space must fall in the range [0,1], negativeroots are not valid solutions to the problem. On the surface, it appearsthat the a must be solved by first solving for case where=1. However, byexpanding the recursions of the a and using the fact that a0 equalszero, a solution that does not require previous a,=0,1, . . . ,n−1exists. The solution is: $a_{i} = {{- 1} + \sqrt{1 + \frac{3i}{N}}}$

[0276] As shown in the following table, the normalized partition valuesfor two, three, and four processors. To calculate the actualpartitioning values, the number of active virtual users is multiplied bythe corresponding table entries. Since a fraction of a user cannot beallocated, a ceiling operation is performed that biases the number ofvirtual users per processor towards the processors whose loadingfunction is less sensitive to perturbations in the number of users.Location Two Processors Three Processors Four Processors a₁${- 1} + {\sqrt{\frac{5}{2}}(0.5811)}$

${- 1} + {\sqrt{2}(0.4142)}$

${- 1} + {\sqrt{\frac{7}{4}}(0.3229)}$

a₂ — ${- 1} + {\sqrt{3}(0.7321)}$

${- 1} + {\sqrt{\frac{5}{2}}(0.5811)}$

a₃ — — ${- 1} + {\sqrt{\frac{13}{4}}(0.8028)}$

[0277] One skilled in the art can appreciate that the load balancing forthe R-matrix results in a non-uniform partitioning of the rows of thefinal matrices over a number of processors. The partition sizes increaseas the partition starting user index increases. When the system isrunning at full capacity (e.g., all co-processors are functional, andthe maximum number of users is processed while still within the boundsof real-time operation), and a co-processor fails, the impact can besignificant.

[0278] This impact can be minimized by allocating the first userpartition to the disabled node. Also the values that would have beencalculated by that node are set to zero. This reduces the effects of thefailed node. By changing which user data is set to zero (e.g., whichusers are assigned to the failed node) the overall errors due to thelack of non-zero output data for that node are averaged over all of theusers, providing a “soft” degradation.

[0279] R, C Values Contiguous in MPIC Processor Memory

[0280] Further, via connection with the crossbar multi-port connector,the multi-processor elements calculating the R-matrix (which depends onthe C-matrix, which in turn depends on the gamma-matrix) can place theresults in a processor element performing the MPIC functions. For oneoptimal solution, the values can be placed in contiguous locationsaccessable (or local with) the MPIC processor. This method allowsadjacent memory addresses for the R and C values, and increasesthroughput via simply incrementing memory pointers rather that using arandom access approach.

[0281] As discussed above, the values of the Γ-matrix elements which arenon-zero need to be determined for efficient storage of the Γ-matrix.For high data rate users, certain elements c_(l)[n] are zero, evenwithin the interval n=0:N−1, N=256. These zero values reduce theinterval over which Γ_(lk)[m] is non-zero. In order to determine theinterval for non-zero values consider the following relations:${\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n = 0}^{N - 1}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}$

[0282] The index j_(l) for the lth virtual user is defined such thatc_(l)[n] is non-zero only over the intervaln=j_(l)N_(l):j_(l)N_(l)+N_(l)−1. Correspondingly, the vector c_(k)[n] isnon-zero only over the interval n=j_(k)N_(k):j_(k)N_(k)+N_(k)−1. Giventhese definitions, Γ_(lk)[m] can be rewritten as${\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n = 0}^{N_{l} - 1}{{c_{l}^{*}\left\lbrack {n + {j_{l}N_{l}}} \right\rbrack} \cdot {c_{k}\left\lbrack {n + {j_{l}N_{l}} - m} \right\rbrack}}}}$

[0283] The minimum value of iii for which Γ_(lk)[m] is non-zero is

m _(min2) =−j _(k) N _(k) +j _(l) N _(l) −N _(k)+1

[0284] and the maximum value of m for which Γ_(lk)[m] is non-zero is

m _(max2) =N _(l)−1−j _(k) N _(k) +j _(l) N _(l)

[0285] The total number of non-zero elements is then $\begin{matrix}{m_{total} \equiv {m_{\max \quad 2} - m_{\min \quad 2} + 1}} \\{= {N_{1} + N_{k} - 1}}\end{matrix}$

[0286] The table below provides a sample of the the number of bytes perl,k virtual-user pair based on 2 bytes per element—one byte for the realpart and one byte for the imaginary part. In other embodiments, thesevalues vary. N_(k) = 256 128 64 32 16 8 4 N₁ = 256 1022 766 638 574 542526 518 128 766 510 382 318 286 270 262 64 638 382 254 90 158 142 134 32574 318 190 26 94 78 70 16 542 286 158 94 62 46 38 8 526 270 142 78 4630 22 4 518 262 134 70 38 22 14

[0287] The memory requirements for storing the Γ-matrix for a givennumber of users at each spreading factor can be determined as describedbelow. For example, for K_(q) virtual users at spreading factorN_(q)≡2^(8−q), q=0:6, where K_(q) is the qth element of the vector K(some elements of K may be zero), the storage requirement can becomputed as follows. Let the table above be stored in matrix M withelements M_(qq). For example, M₀₀=1022, and M₀₁=766. The total memoryrequired by the Γ matrix in bytes is then given by the followingrelation $\begin{matrix}\begin{matrix}{M_{bytes} = {\sum\limits_{q = 0}^{6}\left\{ {{\frac{K_{q}\left( {K_{q} + 1} \right)}{2}M_{qq}} + {\sum\limits_{q^{\prime} = {q + 1}}^{6}{K_{q}K_{q^{\prime}}M_{q\quad q^{\prime}}}}} \right\}}} \\{= {\frac{1}{2}{\sum\limits_{q = 0}^{6}\left\{ {{K_{q}M_{qq}} + {\sum\limits_{q^{\prime} = 0}^{6}{K_{q}K_{q^{\prime}}M_{q\quad q^{\prime}}}}} \right\}}}}\end{matrix} & (27)\end{matrix}$

[0288] Then, continuing the example, for 200 virtual users at spreadingfactor N₀=256, K_(q)=200δ_(q0), which in turn results inM_(bytes)=½K₀(K₀+1)M₀₀=100(201)(1022)=20.5 MB. For 10 384 Kbps users,K_(q)=K₀δ_(q0)+K₆δ_(q6) with K₀=10 and K₆=640, which results in astorage requirement that is given by the following relations:

M _(bytes)=½K ₀(K ₀+1)M ₀₀ +K ₀ K ₆ M ₀₆+½K ₆(K ₆+1)M₆₆=5(11)(1022)+10(640)(518)+320(641)(14)=6.2 MB.

[0289] The Γ-matrix data can be addressed, stored, and accessed asdescribed below. In particular, for each pair (l,k), k>=l, there are 1complex Γ_(lk)[m] values for each value of m, where m ranges fromm_(min2) to m_(max2), and the total number of non-zero elements ism_(total)=m_(max2)−m_(min2)+1. Hence, for each pair (l,k), k>=l, thereexists 2m_(total) time-contiguous bytes.

[0290] In one embodiment, an array structure is created to access thedata, as shown below: struct { int m_min2; int m_max2; int m_total;char * Glk; } G_info[N_VU_MAX][N_VU_MAX];

[0291] The C-matrix data can then be retrieved by utilizing thefollowing exemplary algorithm: m_(min2)=G_info[l][k].m_min2m_(max2)=G_info[l][k].m_max2 N_(g)=L_(g)/N_(c) Nl=m'*N−L_(g)/(2N_(c))for m'=0:1 for q=0:L−1 for q'=0:L−1 γ=m'T+γ_(lq)−γ_(γq')m_(min1)=N1−n_(lq)+n_(kq') m_(max1)=m_(min1)+N_(g) m_(min)=max[m_(min1),m_(min2)] m_(max)=min[m_(min1), m_(min2)] if m_(max)>=m_(min)m_(span)=m_(max)−m_(min)+1 sum1=0.0; ptr1=&G_info[1][k].Glk[m_(min)]ptr2=&g[m_(min)*N_(c)+γ] while m_(span)>0 sum1+=(*ptrl++)*(*ptr2++)m_(span)− end C[m'][l][k][q][q']=sum1 end end end end

[0292] A direct method for calculating the C-matrix (in symmetry) isperformance of the following equation:${C_{k\quad l\quad q^{\prime}}\left\lbrack m^{\prime} \right\rbrack} = {\frac{N_{1}}{N_{k}}{C_{l\quad k\quad q\quad q^{\prime}}^{*}\left\lbrack m^{\prime} \right\rbrack}}$

[0293] Due to symmetry, there are 1.5(K_(v)L)² elements to calculate.Assuming all users are at SF 256, each calculation requires 256 cmacs,or 2048 operations. The probability that a multipath changes in a 10 mstime period is approximately 10/200=0.05 if all users are at 120 kmph.Assuming a mix of user velocities, a reasonable probability is 0.025.Because the C-matrix represents the interaction between two users, theprobability that C-matrix elements change in a 10 ms time period isapproximately 0.10 for all users at 120 kmph, or 0.05 for a mix of usersvelocities. Hence, the GOPS are shown in the following table. Highvelocity Percentage K_(V) users 15(K_(V)L)2 Gops change GOPS 200 100%960,000 1.966 20 39.3 200  50% 960,000 1.966 15 29.5 128 100% 393,2160.805 20 16.1 128  50% 393,216 0.805 15 12.1

[0294] One skilled in the art can appreciate that a fast fouriertransform (FFT) can be used to calculate the correlations for a range ofoffsets, tau, using: $\begin{matrix}{{C_{k\quad l\quad q^{\prime}q}\left\lbrack m^{\prime} \right\rbrack} = {\frac{1}{2\quad N_{l}}{\sum\limits_{n}{{s_{k}\left\lbrack {{n\quad N_{c}} + {m^{\prime}T} + {\hat{\tau}}_{l\quad q} - {\hat{\tau}}_{l\quad q^{\prime}}} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}} \\{= {C_{l\quad k}\left\lbrack {\tau_{l\quad k\quad q\quad q^{\prime}}\left\lbrack m^{\prime} \right\rbrack} \right\rbrack}} \\{{C_{l\quad k}\lbrack\tau\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{s_{k}\left\lbrack {{n\quad N_{c}} + \tau} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}}\end{matrix}$

 τ_(lkqq′) [m′]=m′T+{circumflex over (τ)} _(lq)−{circumflex over(τ)}_(lq′)

[0295] The length of the waveform sk[t] is Lg+255N_(c)=1068 for L_(g)=48and N_(c)=4. This is represented as N_(c) waveforms of lengthL_(g)/N_(c)+255=267. One advantage of this approach is that elements canbe stored for a range of offsets tau so that calculations do not need tobe performed when lags change. For delay spreads of about 4micro-seconds 32 samples need to be stored for each m′.

[0296] The C-matrix elements need be updated when the spreading factorchanges. The spreading factor can change du to AMR codec rate changes,multiplexing of the dedicated channels, or multiplexing of dataservices, to name a few reasons. It is reasonable to assume that 5% ofthe users, hence 10% of the elements, change every 10 ms.

[0297] Gamma-Matrix Generated in FPGA

[0298] The C-matrix elements can be represented in terms of theunderlying code correlations using: $\begin{matrix}{{C_{k\quad l\quad q^{\prime}q}\left\lbrack m^{\prime} \right\rbrack} = {\frac{1}{2N_{l}}{\sum\limits_{n}{{s_{k}\left\lbrack {{n\quad N_{c}} + {m^{\prime}T} + {\hat{\tau}}_{l\quad q} - {\hat{\tau}}_{l\quad q^{\prime}}} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}} \\{= {\sum\limits_{m}{{g\left\lbrack {{m\quad N_{c}} + \tau} \right\rbrack} \cdot {\Gamma_{l\quad k}\lbrack m\rbrack}}}} \\{{\Gamma_{l\quad k}\lbrack m\rbrack} = {\frac{1}{2N_{l}}{\sum\limits_{n}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}}\end{matrix}$

 τ≡m′T+{circumflex over (τ)} _(lq)−{circumflex over (τ)}_(lq′)

[0299] If the length of g[t] is Lg=48 and Nc=4, then the summation overm requires 48/4=12 macs for the real part and 12 macs for the imaginarypart. The total ops is then 48 ops per element. (Compare with 2048operations for the direct method.) Hence for the ease where there are200 virtual users and 20% of the C-matrix needs updating every 10 ms therequired complexity is (960000 cl)(48 ops/cl)(0.20)/(0.010 see)=921.6MOPS. This is the required complexity to compute the C-matrix from theTau-matrix. The cost of computing the Tau-matrix must also beconsidered. The Tau-matrix can be efficiently computed since thefundamental operation is a convolution of codes with elementsconstrained to bc+/−1+/−j. Further, the Tau-matrix can be calculatedusing modulo-2 addition (e.g., XOR) using several method, e.g. registershifting, XOR logic gates, and so on.

[0300] The Gamma matrix (Γ) represents the correlation between thecomplex user codes. The complex code for user 1 is assumed to beinfinite in lenght, but with only N_(l) non-zero values. The non-zerovalues are constrained to bc±1±j. The Γ-matrix can be represented interms of the real and imaginary parts of the complex user codes, and isbased on the relationship: $\begin{matrix}{{\Gamma_{l\quad k}^{XY}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}\left\{ {{M_{lk}^{XY}\lbrack m\rbrack} - {2{N_{lk}^{XY}\lbrack m\rbrack}}} \right\}}} \\{{M_{lk}^{XY}\lbrack m\rbrack} \equiv {\sum\limits_{n}{\cdot {m_{l}^{X}\lbrack n\rbrack} \cdot {m_{k}^{Y}\left\lbrack {n - m} \right\rbrack}}}} \\{{N_{lk}^{XY}\lbrack m\rbrack} \equiv {\sum\limits_{n}{\left( {{\gamma_{l}^{X}\lbrack n\rbrack} \oplus {\gamma_{k}^{Y}\left\lbrack {n - m} \right\rbrack}} \right) \cdot {m_{l}^{X}\lbrack n\rbrack} \cdot {m_{k}^{Y}\left\lbrack {n - m} \right\rbrack}}}}\end{matrix}$

[0301] which can be performed using a dual-set of shift registers and alogical circuit containing modulo-2 (e.g., Exclusive-OR “XOR”) logicelements. Further, one skilled in the art can appreciate that such alogic device can be implemented in a field programmable gate array,which can be programmed via the host controller, a compute element, orother device including an application specific integrated circuit.Further, the FPGA can be progammed via the RACEway™ bus, for example.

[0302] The above shift registers together with a summation devicecalculates the functions M_(lk) ^(XY)[m] and N_(lk) ^(XY)[m]. Theremaining calculations to form Γ_(lk) ^(XY)[m] and subsequentlyΓ_(lk)[m] can be performed in software. Note that the four functionsΓ_(lk) ^(XY)[m] corrsponding to X, Y=R, I which are components of can becalculated in parallel. For K_(v)=200 virtual users, and assuming that10% of all (l, k) pairs must be calculated in 2 ms, then for real-timeoperation we must calculate 0.10(200)²=4000 elements (all shifts) in 2ms, or about 2M elements (all shifts) per second. For K_(v)=128 virtualusers the requirement drops to 0.8192M elements (all shifts) per second.

[0303] In what has been presented the elements are calculated for all512 shifts. Not all of these shifts are needed, so it is possible toreduce the number of calculations per elements. The cost is increaseddesign complexity.

[0304] Therefore, a possible loading scenaio for performing short-codemultiple user detection on the hardware described herein is illustratedin FIG. 11. A processor board 118 with four compute elements 220 can beused as shown. Three of the compute nodes (e.g., 220 a-220 c) can beused to calculate the C-matrix and R-matrix. One of the compute nodes(e.g., 220 d) can be used for multiple-stage decision-feedbackinterference cancellation (MDFIC) techniques. The Tau-Matrix andR-Matrix is calculated using FPGA's that can be programmed by the hostcontroller 203, or ASICs. Further, multiuser amplitude estimation isperformed within the modem card 112.

[0305] Long-Code Processing

[0306] Therefore it can be appreciated by one skilled in the art thatshort-code MUD can be performed using the system architecture describedherein. FIG. 12 shows a preferred embodiment for long-code MUDprocessing. In this embodiment, each frame of data is processed threetimes by the MUD processor, although it can be recognized that multipleprocessors can perform the iterative nature of the embodiment. Duringthe first pass, only the control channels are respread which the maximumratio combination (MRC) and MUD processing is performed on the datachannels. During subsequent passes, data channels are processedexclusively. New y (i.e., soft decisions) and b (i.e., hard decisions)data are derived as shown in the diagram.

[0307] Amplitude ratios and amplitudes are determined via the DSP (e.g.,element 900, or a DSP otherwise coupled with the processor board 118 andreceiver 110), as well as certain waveform statistics. These values(e.g., matrices and vectors) are used by the MUD processor in variousways. The MUD processor is decomposed into four stages that closelymatch the structure of the software simulation: Alpha Calculation andRespread 1302, raised-cosine filtering 1304, de-spreading 1306, and MRC1308. Each pass through the MUD processor is equivalent to oneprocessing stage of the software implementation. The design is pipelinedand “parallelized.” In the illustrated embodiment, the clock speed canbe 132 MHz resulting in a throughput of 2.33 ms/frame, however, theclock rate and throughput varies depending on the requirements. Theillustrated embodiment allows for three-pass MUD processing withadditional overhead from external processing, resulting in a 4-timesreal-time processing throughput.

[0308] The alpha calculation and respread operations 1302 are carriedout by a set of thirty-two processing elements arranged in parallel.These can be processing elements within an ASIC, FPGA, PLD or other suchdevice, for example. Each processing element processes two users of fourfingers each. Values for b are stored in a double-buffered lookup table.Values of a(hat) and ja(hat) are pre-multiplied with beta by an externalprocessor and stored in a quad-buffered lookup table. The alphacalculation state generated the following values for each finger, wheresubscripts indicate antenna identifier:

α₀=β₀·(C·â ₀ −jC·jâ ₀)

jα ₀=β₀·(jC·â ₀ +C·jâ ₀)

α1=β₁·(C·â ₁ −jC·jâ ₁)

jα ₁=β₁·(jC·â ₁ +C·jâ ₁)

[0309] These values are accumulated during the serial processing cycleinto four independent 8-times oversampling buffers. There are eightmemory elements in each buffer and the element used is determined by thesub-chip delay setting for each finger.

[0310] Once eight fingers have been accumulated into the oversamplingbuffer, the data is passed into set of four independent adder-trees.These adder-trees each termination in a single output, completing therespread operation.

[0311] The four raised-cosine filters 1304 convolve the alpha data witha set of weights determined by the following equation:${g_{rc}(t)} = \frac{\sin \quad {\left( {\pi \quad \frac{1}{t}} \right) \cdot \cos}\quad \left( {\alpha \quad \pi \quad \frac{1}{T}} \right)}{\pi \quad \frac{1}{t}\left( {1 - \left( {2\alpha \quad \frac{1}{T}} \right)^{2}} \right)}$

[0312] The filters can be implemented with 97 taps with odd symmetry.The filters illustrated run at 8-times the chip rate, however, otherrates are possible. The filters can be implemented in a variety ofcompute elements 220, or other devices such as ASICs, FPGAs for example.

[0313] The despread function 1306 can be performed by a set ofthirty-two processing elements arranged in parallel. Each processingelement serially processes two users of four fingers each.

[0314] For each finger, one chip value out of eight, selected based onthe sub-chip delay, is accepted from the output of the raised-cosinefilter. The despread state performs the following calculations for eachfinger (subscripts indicate antenna): $\begin{matrix}{y_{0} = {{\sum\limits_{0}^{{SF} - 1}{C \cdot r_{0}}} + {j\quad {C \cdot j}\quad r_{0}}}} \\{{j\quad y_{0}} = {{\sum\limits_{0}^{{SF} - 1}{{C \cdot j}\quad r_{0}}} - {j\quad {C \cdot r_{0}}}}} \\{y_{1} = {{\sum\limits_{0}^{{SF} - 1}{C \cdot r_{1}}} + {j\quad {C \cdot j}\quad r_{1}}}} \\{{j\quad y_{1}} = {{\sum\limits_{0}^{{SF} - 1}{{C \cdot j}\quad r_{1}}} - {j\quad {C \cdot r_{1}}}}}\end{matrix}$

[0315] The MRC operations are carried out by a set of four processingelements arranged in parallel, such as the compute elements 220 forexample. Each processor is capable of serially processing eight users offour fingers each. Values for y are stored in a double-buffered lookuptable. Values for b are derived from the MSB of the y data. Note thatthe b data used in the MUD stage is independent of the b data used inthe respread stage. Values of â and jâ<are pre-multiplied with β by anexternal processor and stored in a quad-buffered lookup table. Also,Σ(â²+jâ²) for each channel is stored in a quad-buffered table.

[0316] The output stage contains a set of sequential destination bufferpointers for each channel. The data generated by each channel, on a slotbasis, is transferred to the RACEway™ destination indicated by thesebuffers. The first word of each of these transfers will contain acounter in the lower sixteen bits indicating how many y values weregenerated. The upper sixteen bits will contain the constant value0xAA55. This will allow the DSP to avoid interrupts by scanning thefirst word of each buffer.

[0317] In addition, the DSP_UPDATE register contains a pointer to singleRACEway™ location. Each time a slot or channel data is transmitted, aninternal counter is written to this location. The counter is limited to10 bits and will wrap around with a terminal count value of 1023.

[0318] The method of operation for the long-code multiple user detectionalgorithm (LCMUD) is as follows. Spread factor for four-channelsrequires significant amount of data transfer. In order to limit the gatecount of the hardware implementation, processing an SF4 channel canresult in reduced capability.

[0319] A SF4 user can be processed on certain hardware channels. Whenone of these special channels is operating on an SF4 user, the nextthree channels are disabled and are therefore unavailable forprocessing. This relationship is as shown in the following table: SF4Chan Disabled Channels SF4 Chan Disabled Channels 0 1, 2, 3 32 33, 34,35 4 5, 6, 7 36 37, 38, 39 8 9, 10, 11 40 41, 42, 43 12 12, 14, 15 4445, 46, 47 16 17, 18, 19 48 49, 50, 51 20 21, 22, 23 52 53, 54, 55 2425, 26, 27 56 57, 58, 59 28 29, 30, 31 60 61, 62, 63

[0320] The default y and b data buffers do not contain enough space forSF4 data. When a channel is operating on SF4 data, the y and b buffersextend into the space of the next channel in sequence. For example, ifchannel 0 is processing SF data, the channel 0 and channel 1 b buffersare merged into a single large buffer of 0x40 32-bit words. The ybuffers are merged similarly.

[0321] In typical operation, the first pass of the LCMUD algorithm willrespread the control channels in order to remove control interference.For this pass, the b data for the control channels should be loaded intoBLUT while the y data for data channels should be loaded into YDEC. Eachchannel should be configured to operate at the spread factor of the datachannel stored into the YDEC table.

[0322] Control channels are always operated at SF 256, so it is likelythat the control data will need to be replicated to match the datachannel spread factor. For example, each bit (b entry) of control datawould be replicated 64 times if that control channel were associatedwith an SF 4 data channel.

[0323] Each finger in a channel arrives at the receiver with a differentdelay. During the Respread operation, this skew among the fingers isrecreated. During the MRC stage of MUD processing, it is necessary toremove this skew and realign the fingers of each channel.

[0324] This is accomplished in the MUD processor by determining thefirst bit available from the most delayed finger and discarding allprevious bits from all other fingers. The number of bits to discard canbe individually programmed for each finger with the Discard field of theMUDPARAM registers.

[0325] This operation will typically result in a ‘short’ first slot ofdata. This is unavoidable when the MUD processor is first initializedand should not create any significant problems. The entire first slot ofdata can be completely discarded if ‘short’ slots are undesirable.

[0326] A similar situation will arise each time processing is begun on aframe of data. To avoid losing data, it is recommended that a partialslot of data from the previous frame be overlapped with the new frame.Trimming any redundant bits created this way can be accomplished withthe Discard register setting or in the system DSP. In order to limitmemory requirements, the LCMUD FPGA processes one slot of data at atime. Doubling buffering is used for b and y data so that processing cancontinue as data is streamed in. Filling these buffers is complicated bythe skew that exists among fingers in a channel.

[0327]FIG. 13 illustrates the skew relationship among fingers in achannel and among the channels themselves. The illustrated embodimentallows for 20 us (77.8 chips) of skew among fingers in a channel andcertain skew among channels, however, in other embodiments these skewallowances vary.

[0328] There are three related problems that are introduced by skew:Identifying frame & slot boundaries, populating b and y tables andchanging channel constants.

[0329] Because every finger of every channel can arrive at a differenttime, there are no universal frame and slot boundaries. The DSP mustselect an arbitrary reference point. The data stored in b & y tables islikely to come from two adjacent slots.

[0330] Because skew exists among fingers in a channel, it is not enoughto populate the b & y tables with 2,560 sequential chips of data. Theremust be some data overlap between buffers to allow lagging channels toaccess “old” data. The amount of overlap can be calculated dynamicallyor fixed at some number greater than 78 and divisible by four (e.g. 80chips). The starting point for each register is determined by the ChipAdvance field of the MUDPARAM register.

[0331] A related problem is created by the significant skew amongchannels. As can be seen in FIG. 13, Channel 0 is receiving Slot 0 whileChannel 1 is receiving Slot 2. The DSP must take this skew into accountwhen generating the b and y tables and temporally align channel data.

[0332] Selecting an arbitrary “slot” of data from a channel implies thatchannel constants tied to the physical slot boundaries may change whileprocessing the arbitrary slot. The Constant Advance field of theMUDPARAM register is used to indicate when these constants shouldchange.

[0333] Registers affected this way are quad-buffered. Before dataprocessing begins, at least two of these buffers should be initialized.During normal operation, one additional buffer is initialized for eachslot processed. This system guarantees that valid constants data willalways be available.

[0334] The following two tables shown the long-code MUD FPGA memory mapand control/status register: Start Addr End Addr Name Description0000_0000 0000_0000 CSR Control & Status Register 0000_0008 0000_000CDSP_UPDATE Route & Address for DSP updating 0001_0000 0001_FFFF MUDPARAMMUD Parameters 0002_0000 0002_FFFF CODE Spreading Codes 0003_00000004_FFFF BLUT Respread: b Lookup Table 0005_0000 0005_FFFF BETA_ARespread: Beta * a_hat Lookup Table 0006_0000 0007_FFFF YDEC MUD & MRC:y Lookup Table 0008_0000 0008_FFFF ASQ MUD & MRC: Sum a_hat squared LUT000A_0000 000A_FFFF OUTPUT Output Routes & Addresses

[0335] Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name ReservedR/W RO Reset X X X X X X X X X X X X X X X X Bit 15 14 13 12 11 10 9 8 76 5 4 3 2 1 0 Name Reserved YB CBUF A1 A0 R1 R0 Lst Rst R/W RO RO RO RORO Rw Rw Rw Rw Reset X X X X X X X 0 0 0 0 0 0 0 0 0

[0336] The register YB indicates which of two y and b buffers are inuse. If the system is currently not processing, YB indicates the bufferthat will be used when processing is initiated.

[0337] CBUF indicates which of four round-robin buffers for MUDconstants (a{circumflex over ( )} beta) is currently in use. Finger skewwill result in some fingers using a buffer one in advance of thisindicator. To guarantee that valid data is always available, two fullbuffers should be initialized before operation begins.

[0338] If the system is currently not processing, CBUF indicates thebuffer that will be used when processing is restarted. It is technicallypossible to indicate precisely which buffer is in use for each finger inboth the Respread and Despread processing stages. However, this wouldrequire thirty-two 32-bit registers. Implementing these registers wouldbe costly, and the information is of little value.

[0339] A1 and A0 indicate which y and b buffers are currently beingprocessed. A1 and A0 will never indicate ‘1’ at the same time. Anindication of ‘0’ for both A1 and A0 means that MUD processor is idle.

[0340] R1 and R0 are writable fields that indicate to the MUD processorthat data is available. R1 corresponds to y and b buffer 1 and R0corresponds to y and b buffer 0. Writing a ‘1’ into the correct registerwill initiate MUD processing. Note that these buffers follow strictround-robin ordering. The YB register indicates which buffer should beactivated next.

[0341] These registers will be automatically reset to ‘0’ by the MUDhardware once processing is completed. It is not possible for theexternal processor to force a ‘0’ into these registers.

[0342] A ‘1’ in this bit indicates that this is the last slot of data ina frame. Once all available data for the slot has been processed, theoutput buffers will be flushed.

[0343] A ‘1’ in this bit will place the MUD processor into a resetstate. The external processor must manually bring the MUD processor outof reset by writing a ‘0’ into this bit.

[0344] DSP_UPDATE is arranged as two 32-bit registers. A RACEway™ routeto the MUD DSP is stored at address 0x0000_(—)0008. A pointer to astatus memory buffer is located at address 0x0000_(—)000C.

[0345] Each time the MUD processor writes a slot of channel data to acompletion buffer, an incrementing count value is written to thisaddress. The counter is fixed at 10 bits and will wrap around after aterminal count of 1023.

[0346] A quad-buffered version of the MUD parameter control registerexists for each finger to be processed. Execution begins with buffer 0and continues in round-robin fashion. These buffers are used insynchronization with the MUD constants (Beta * a_hat, etc.) buffers.Each finger is provided with an independent register to allowindependent switching of constant values at slot and frame boundaries.The following table shows offsets for each MUD channel: Offset User0x0000 0 0x0040 1 0x0080 2 0x00C0 3 0x0100 4 0x0140 5 0x0180 6 0x0100 70x0200 8 0x0240 9 0x0280 10 0x02C0 11 0x0300 12 0x0340 13 0x0380 140x03C0 15 0x0400 16 0x0440 17 0x0480 18 0x04C0 19 0x0500 20 0x0540 210x0580 22 0x05C0 23 0x0600 24 0x0640 25 0x0680 26 0x06C0 27 0x0700 280x0740 29 0x0780 30 0x07C0 31 0x0800 32 0x0840 33 0x0880 34 0x08C0 350x0900 36 0x0940 37 0x0980 38 0x09C0 39 0x0A00 40 0x0A40 41 0x0A80 420x0AC0 43 0x0B00 44 0x0B40 45 0x0B80 46 0x0BC0 47 0x0C00 48 0x0C40 490x0CS0 50 0x0CC0 51 0x0D00 52 0x0D40 53 0x0080 54 0x0DC0 55 0x0E00 560x0E40 57 0x0ES0 58 0x0EC0 59 0x0F00 60 0x0F40 61 0x0F80 62 0x0FC0 63

[0347] The following table shows buffer offsets within each channel:Offset Finger Buffer 0x0000 0 0 0x0004 1 0x0008 2 0x000C 3 0x0010 1 00x0014 1 0x0018 2 0x001C 3 0x0020 2 0 0x0024 1 0x0028 2 0x002C 3 0x00303 0 0x0034 1 0x0038 2 0x003C 3

[0348] The following table shown details of the control register: Bit 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Spread Factor SubchipDelay Discard R/W RW RW RW Reset X X X X X X X X X X X X X X X X Bit 1514 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Chip Advance Constant AdvanceR/W RW RW Reset X X X X X X X X X X X X X X X X

[0349] The spread factor field determines how many chip samples are usedto generate a data bit. In the illustrated embodiment, all fingers in achannel have the same spread factor setting, however, it can beappreciated by one skilled in the art that such constant factor settingcan be variable in other embodiments. The spread factor is encoded intoa 3-bit value as shown in the following table: SF Factor Spread Factor000 256 001 128 010 64 011 32 100 16 101 8 110 4 111 RESERVED

[0350] The field specifies the sub-chip delay for the finger. It is usedto select one of eight accumulation buffers prior to summing all Alphavalues and passing them into the raised-cosine filter.

[0351] Discard determines how many MUD-processed soft decisions (yvalues) to discard at the start of processing. This is done so that thefirst y value from each finger corresponds to the same bit. After thefirst slot of data is processed, the Discard field should be set tozero.

[0352] The behavior of the discard field is different than that of otherregister fields. Once a non-zero discard setting is detected, any newdiscard settings from switching to a new table entry are ignored untilthe current discard count reaches zero. After the count reaches zero, anew discard setting may be loaded the next time a new table entry isaccessed.

[0353] All fingers within a channel will arrive at the receiver withdifferent delays. Chip Advance is used to recreate this signal skewduring the Respread operation. Y and b buffers are arranged with olderdata occupying lower memory addresses. Therefore, the finger with theearliest arrival time has the highest value of chip advance. ChipAdvanced need not be a multiple of Spread Factor.

[0354] Constant advance indicates on which chip this finger shouldswitch to a new set of constants (e.g. a{circumflex over ( )}) and a newcontrol register setting. Note that the new values take effect on thechip after the value stored here. For example, a value of 0x0 wouldcause the new constants to take effect on chip 1. A value of 0xFF wouldcause the new constants to take effect on chip 0 of the next slot. The blookup tables are arranged as shown in the following table. B valueseach occupy two bits of memory, although only the LSB is utilized byLCMUD hardware. Offset Buffer 0x0000  U0 B0 0x0020  U1 B0 0x0040  U0 B10x0060  U1 B1 0x0080  U2 B0 0x00A0  U3 B0 0x00C0  U2 B1 0x00E0  U3 B10x0100  U4 B0 0x0120  U5 B0 0x0140  U4 B1 0x0160  U5 B1 0x0180  U6 B00x01A0  U7 B0 0x01C0  U6 B1 0x01E0  U7 B1 0x0200  U8 B0 0x0220  U9 B00x0240  U8 B1 0x0260  U9 B1 0x0280 U10 B0 0x02A0 U11 B0 0x02C0 U10 B10x02E0 U11 B1 0x0300 U12 B0 0x0320 U13 B0 0x0340 U12 B1 0x0360 U13 B10x0380 U14 B0 0x03A0 U15 B0 0x03C0 U14 B1 0x03E0 U15 B1 0x0400 U16 B00x0420 U17 B0 0x0440 U16 B1 0x0460 U17 B1 0x0480 U18 B0 0x04A0 U19 B00x04C0 U18 B1 0x04E0 U19 B1 0x0500 U20 B0 0x0520 U21 B0 0x0540 U20 B10x0560 U21 B1 0x0580 U22 B0 0x05A0 U23 B0 0x05C0 U22 B1 0x05E0 U23 B10x0600 U24 B0 0x0620 U25 B0 0x0640 U24 B1 0x0660 U25 B1 0x0680 U26 B00x06A0 U27 B0 0x06C0 U26 B1 0x06E0 U27 B1 0x0700 U28 B0 0x0720 U29 B00x0740 U28 B1 0x0760 U29 B1 0x0780 U30 B0 0x07A0 U31 B0 0x07C0 U30 B10x07E0 U31 B1 0x0800 U32 B0 0x0820 U33 B0 0x0840 U32 B1 0x0860 U33 B10x0880 U34 B0 0x08A0 U35 B0 0x08C0 U34 B1 0x08E0 U35 B1 0x0900 U36 B00x0920 U37 B0 0x0940 U36 B1 0x0960 U37 B1 0x0980 U38 B0 0x09A0 U39 B00x09C0 U38 B1 0x09E0 U39 B1 0x0A00 U40 B0 0x0A20 U41 B0 0x0A40 U40 B10x0A60 U41 B1 0x0A50 U42 B0 0x0AA0 U43 B0 0x0AC0 U42 B1 0x0AE0 U43 B10x0B00 U44 B0 0x0B20 U45 B0 0x0B40 U44 B1 0x0B60 U45 B1 0x0B80 U46 B00x0BA0 U47 B0 0x0BC0 U46 B1 0x0BE0 U47 B1 0x0C00 U48 B0 0x0C20 U49 B00x0C40 U48 B1 0x0600 U49 B1 0x0C80 U50 B0 0x0CA0 U51 B0 0x0CC0 U50 B10x0CE0 U51 B1 0x0D00 U52 B0 0x0D20 U53 B0 0x0D40 U52 B1 0x0D60 U53 B10x0D80 U54 B0 0x0DA0 U55 B0 0x0DC0 U54 B1 0x0DE0 U55 B1 0x0E00 U56 B00x0E20 U57 B0 0x0E40 U56 B1 0x0E60 U57 B1 0x0E80 U58 B0 0x0EA0 U59 B00x0EC0 U58 B1 0x0EE0 U59 B1 0x0F00 U60 B0 0x0F20 U61 B0 0x0F40 U60 B10x0F60 U61 B1 0x0F80 U62 B0 0x0FA0 U63 B0 0x0FC0 U62 B1 0x0FE0 U63 B1

[0355] The following table illustrates how the two-bit values are packedinto 32-bit words. Spread Factor 4 channels require more storage spacethan is available in a single channel buffer. To allow for SF4processing, the buffers for an even channel and the next highest oddchannel are joined together. The even channel performs the processingwhile the odd channel is disabled. Bit 31 30 29 28 27 26 25 24 23 22 2120 19 18 17 16 Name b(0) b(1) b(2) b(3) b(4) b(5) b(6) b(7) Bit 15 14 1312 11 10 9 8 7 6 5 4 3 2 1 0 Name b(8) b(9) b(10) b(11) b(12) b(13)b(14) b(15)

[0356] The beta*a-hat table contains the amplitude estimates for eachfinger pre-multiplied by the value of Beta. The following table showsthe memory mappings for each channel. Offset User 0x0000 0 0x0080 10x0100 2 0x0180 3 0x0200 4 0x0280 5 0x0300 6 0x0380 7 0x0400 8 0x0480 90x0500 10 0x0580 11 0x0600 12 0x0680 13 0x0700 14 0x0780 15 0x0800 160x0880 17 0x0900 18 0x0980 19 0x0A00 20 0x0A80 21 0x0B00 22 0x0B80 230x0C00 24 0x0C80 25 0x0D00 26 0x0D80 27 0x0E00 28 0x0E80 29 0x0F00 300x0F80 31 0x1000 32 0x1080 33 0x1100 34 0x1180 35 0x1200 36 0x1280 370x1300 38 0x1380 39 0x1400 40 0x1480 41 0x1500 42 0x1580 43 0x1600 440x1680 45 0x1700 46 0x1780 47 0x1800 48 0x1880 49 0x1900 50 0x1980 510x1A00 52 0x1A80 53 0x1B00 54 0x1B80 55 0x1C00 56 0x1C80 57 0x1D00 580x1D80 59 0x1E00 60 0x1E80 61 0x1F00 62 0x1F80 63

[0357] The following table shows buffers that are distributed for eachchannel: Offset User Buffer 0x00 0 0x20 1 0x40 2 0x80 3

[0358] The following table shows a memory mapping for individual fingersof each antenna. Offset Finger Antenna 0x00 0 0 0x04 1 0x08 2 0x0C 30x10 0 1 0x14 1 0x18 2 0x1C 3

[0359] The y (soft decisions) table contains two buffers for eachchannel. Like the b lookup table, an even and odd channel are bondedtogether to process SF4. Each y data value is stored as a byte. The datais written into the buffers as packed 32-bit words. Offset Buffer 0x0000 U0 B0 0x0200  U1 B0 0x0400  U2 B1 0x0600  U3 B1 0x0800  U0 B0 0x0A00 U1 B0 0x0C00  U2 B1 0x0E00  U3 B1 0x0000  U4 B0 0x0200  U5 B0 0x0400 U6 B1 0x0600  U7 B1 0x0800  U4 B0 0x0A00  U5 B0 0x0C00  U6 B1 0x0E00 U7 B1 0x0000  U8 B0 0x0200  U9 B0 0x0400 U10 B1 0x0600 U11 B1 0x0800 U8 B0 0x0A00  U9 B0 0x0C00 U10 B1 0x0E00 U11 B1 0x0000 U12 B0 0x0200U13 B0 0x0400 U14 B1 0x0600 U15 B1 0x0800 U12 B0 0x0A00 U13 B0 0x0C00U14 B1 0x0E00 U15 B1 0x4000 U16 B0 0x4200 U17 B0 0x4400 U18 B1 0x4600U19 B1 0x4800 U16 B0 0x4A00 U17 B0 0x4C00 U18 B1 0x4E00 U19 B1 0x5000U20 B0 0x5200 U21 B0 0x5400 U22 B1 0x5600 U23 B1 0x5800 U20 B0 0x5A00U21 B0 0x5C00 U22 B1 0x5E00 U23 B1 0x6000 U24 B0 0x6200 U25 B0 0x6400U26 B1 0x6600 U27 B1 0x6800 U24 B0 0x6A00 U25 B0 0x6C00 U26 B1 0x6E00U27 B1 0x7000 U28 B0 0x7200 U29 B0 0x7400 U30 B1 0x7600 U31 B1 0x7800U28 B0 0x7A00 U29 B0 0x7C00 U30 B1 0x7E00 U31 B1 0x8000 U32 B0 0x8200U33 B0 0x8400 U34 B1 0x8600 U35 B1 0x8800 U32 B0 0x8A00 U33 B0 0x8C00U34 B1 0x8E00 U35 B1 0x9000 U36 B0 0x9200 U37 B0 0x9400 U38 B1 0x9600U39 B1 0x9800 U36 B0 0x9A00 U37 B0 0x9C00 U38 B1 0x9E00 U39 B1 0xA000U40 B0 0xA200 U41 B0 0xA400 U42 B1 0xA600 U43 B1 0xA800 U40 B0 0xAA00U41 B0 0xAC00 U42 B1 0xAE00 U43 B1 0xB000 U44 B0 0xB200 U45 B0 0xB400U46 B1 0xB600 U47 B1 0xB800 U44 B0 0xBA00 U45 B0 0xBC00 U46 B1 0xBE00U47 B1 0xC000 U48 B0 0xC200 U49 B0 0xC400 U50 B1 0xC600 U51 B1 0xC800U48 B0 0xCA00 U49 B0 0xCC00 U50 B1 0xCE00 U51 B1 0xD000 U52 B0 0xD200U53 B0 0xD400 U54 B1 0xD600 U55 B1 0xD800 U52 B0 0xDA00 U53 B0 0xDC00U54 B1 0xDE00 U55 B1 0xE000 U56 B0 0xE200 U57 B0 0xE400 U58 B1 0xE600U59 B1 0xE800 U56 B0 0xEA00 U57 B0 0xEC00 U58 B1 0xEE00 U59 B1 0xF000U60 B0 0xF200 U61 B0 0xF400 U62 B1 0xF600 U63 B1 0xF800 U60 B0 0xFA00U61 B0 0xFC00 U62 B1 0xFE00 U63 B1

[0360] The sum of the a-hat squares is stored as a 16-bit value. Thefollowing table contains a memory address mapping for each channel.Offset User 0x0000 0 0x0020 1 0x0040 2 0x0060 3 0x0080 4 0x00A0 5 0x00C06 0x00E0 7 0x0100 8 0x0120 9 0x0140 10 0x0160 11 0x0180 12 0x01A0 130x01C0 14 0x01E0 15 0x0200 16 0x0220 17 0x0240 18 0x0260 19 0x0280 200x02A0 21 0x02C0 22 0x02E0 23 0x0300 24 0x0320 25 0x0340 26 0x0360 270x0380 28 0x03A0 29 0x03C0 30 0x03E0 31 0x0400 32 0x0420 33 0x0440 340x0460 35 0x0480 36 0x04A0 37 0x04C0 38 0x04E0 39 0x0500 40 0x0520 410x0540 42 0x0560 43 0x0580 44 0x05A0 45 0x05C0 46 0x05E0 47 0x0600 480x0620 49 0x0640 50 0x0660 51 0x0680 52 0x06A0 53 0x06C0 54 0x06E0 550x0700 56 0x0720 57 0x0740 58 0x0760 59 0x0780 60 0x07A0 61 0x07C0 620x07E0 63

[0361] Within each buffer, the value for antenna 0 is stored at addressoffset 0x0 with the value for antenna one stored at address offset 0x04.The following table demonstrates a mapping for each finger. Offset UserBuffer 0x00 0 0x08 1 0x10 2 0x1C 3

[0362] Each channel is provided a RACEway™ route on the bus, and a baseaddress for buffering output on a slot basis. Registers for controllingbuffers are allocated as shown in the following two tables. Externaldevices are blocked from writing to register addresses marked asreserved. Offset User 0x0000 0 0x0020 1 0x0040 2 0x0060 3 0x0080 40x00A0 5 0x00C0 6 0x00E0 7 0x0100 8 0x0120 9 0x0140 10 0x0160 11 0x018012 0x01A0 13 0x01C0 14 0x01E0 15 0x0200 16 0x0220 17 0x0240 18 0x0260 190x0280 20 0x02A0 21 0x02C0 22 0x02E0 23 0x0300 24 0x0320 25 0x0340 260x0360 27 0x0380 28 0x03A0 29 0x03C0 30 0x03E0 31 0x0400 32 0x0420 330x0440 34 0x0460 35 0x0480 36 0x04A0 37 0x04C0 38 0x04E0 39 0x0500 400x0520 41 0x0540 42 0x0560 43 0x0580 44 0x05A0 45 0x05C0 46 0x05E0 480x0600 48 0x0620 49 0x0640 50 0x0660 51 0x0680 52 0x06A0 53 0x06C0 540x06E0 55 0x0700 56 0x0720 57 0x0740 58 0x0760 59 0x0780 60 0x07A0 610x07C0 62 0x07E0 63

[0363] Offset Entry 0x0000 Route to Channel Destination 0x0004 BaseAddress for Buffers 0x0008 Buffers 0x000C RESERVED 0x0010 RESERVED0x0014 RESERVED 0x0018 RESERVED 0x001C RESERVED

[0364] Slot buffer size is automatically determined by the channelspread factor. Buffers are used in round-robin fashion and all buffersfor a channel must be arranged contiguously. The buffers controlregister determines how many buffers are allocated for each channel. Asetting of 0 indicates one available buffer, a setting of 1 indicatestwo available buffers, and so on.

[0365] Methods for Estimating Symbols Embodied in Short-Code UserWaveforms

[0366] As discussed above, systems according to the invention performmulti-user detection by determining correlations among the userchannel-corrupted waveforms and storing these correlations as elementsof the R-matrices. The correlations are updated in real time to trackcontinually changing channel characteristics. The changes can stem fromchanges in user code correlations, which depend on the relative lagamong various user multi-path components, as well as from the muchfaster variations of the Rayleigh-fading multi-path amplitudes. Therelative lags among multi-path components can change with a timeconstant, for example, of about 400 ms whereas the multi-path amplitudescan vary temporally with a time constant of, for example, 1.33 ms. TheR-matrices are used to cancel the multiple access interference throughthe Multi-stage Decision-Feedback Interference Cancellation (MDFIC)technique.

[0367] In the preceding discussion and those that follow, the ternphysical user refers to a CDMA signal source, e.g., a user cellularphone, modem or other CDMA signal source, the transmitted waveforms fromwhich are processed by a base station and, more particularly, by MUDprocessing card 118. In the illustrated embodiment, each physical useris considered to be composed of a one or more virtual users and, moretypically, a plurality of virtual users.

[0368] A virtual user is deemed to “transmit” a single bit per symbolperiod, where a symbol period can be, for example, a time duration of256 chips ({fraction (1/15)} ms). Thus, the number of virtual users, fora given physical user, is equal to the number of bits transmitted in asymbol period. In the illustrated embodiment, each physical user isassociated with at least two virtual users, one of which corresponds toa Dedicated Physical Control Channel (DPCCH) and the other of whichcorresponds to a Dedicated Physical Data Channel (DPDCH). Otherembodiments may provide for a single virtual user per physical user, aswell, of course, to three or more virtual users per physical user.

[0369] In the illustrated embodiment, when a Spreading Factor (SF)associated with a physical user is less than 256, the J=256/SF data bitsand one control bit are transmitted per symbol period. Hence, for ther^(th) physical user with data-channel spreading factor SF_(i), thereare a total of 1+256/SF_(i) virtual users. The total number of virtualusers can then be denoted by: $\begin{matrix}{K_{v} \equiv {\sum\limits_{i = 1}^{K}\left\lbrack {1 + \frac{256}{{SF}_{r}}} \right\rbrack}} & (1)\end{matrix}$

[0370] The waveform transmitted by the rth physical user can be writtenas: $\begin{matrix}\begin{matrix}{{x_{r}\lbrack t\rbrack} = {\sum\limits_{k = 1}^{1 + J_{r}}{\beta_{k}{\sum\limits_{m}{{s_{k}\left\lbrack {t - {m\quad T}} \right\rbrack}{b_{k}\lbrack m\rbrack}}}}}} \\{{s_{k}\lbrack t\rbrack} \equiv {\sum\limits_{p = 0}^{N - 1}{{h\left\lbrack {t - {p\quad N_{c}}} \right\rbrack}{c_{k}\lbrack p\rbrack}}}}\end{matrix} & (2)\end{matrix}$

[0371] where t is the integer time sample index, T=NN_(c) represents thedata bit duration, N=256 represents short-code length, N_(c) is thenumber of samples per chip, and where β_(k)=β_(c) if the kth virtualuser is a control channel and β_(k)=β_(d) if the kth virtual user is adata channel. The multipliers β_(c) and β_(d) are utilized to select therelative amplitudes of the control and data channels. In the illustratedembodiment, at least one of the above constants equals 1 for any givensymbol period, m.

[0372] The waveform sk[t], which is herein referred to as thetransmitted signature waveform for the kth virtual user, is generated bythe illustrated system by passing the spread code sequence ck[n] througha root-raised-cosine pulse shaping filter h[t]. When the kth virtualuser corresponds to a data user with a spreading factor that is lessthan 256, the code ck[n] retains a length of 256, but only Nk of these256 elements are non-zero, where Nk is the spreading factor for the kthvirtual user. The non-zero values are extracted from the codeC_(ch,256,64)[n]·s_(sh)[n].

[0373] The baseband received signal can be written as: $\begin{matrix}{{{r\lbrack t\rbrack} = {{\sum\limits_{k = 1}^{K_{v}}{\sum\limits_{m}{{{\overset{\sim}{s}}_{k}\left\lbrack {t - {mT}} \right\rbrack}{b_{k}\lbrack m\rbrack}}}} + {w\lbrack t\rbrack}}}{{s_{k}\lbrack t\rbrack} \equiv {\sum\limits_{q^{\prime} = 1}^{L}{a_{kq}{s_{k}\left\lbrack {t - \tau_{{kq}^{\prime}}} \right\rbrack}}}}} & (3)\end{matrix}$

[0374] where w[t] is receiver noise, {tilde over (s)}_(k)[t] is thechannel-corrupted signature waveform for virtual user k, L is the numberof multipath components, and a_(kq′) are the complex multipathamplitudes. The amplitude ratios β_(k) are incorporated into theamplitudes a_(kq′). If k and l are two virtual users that correspond tothe same physical user then, aside from scaling factors β_(k) andβ_(l′), a_(kq′) and a_(lq′) are equal. This is due to the fact that thesignal waveforms of all virtual users corresponding to the same physicaluser pass through the same channel. Further, the waveform s_(k)[t]represents the received signature waveform for the k^(th) virtual user,and it differs from the transmitted signature waveform given in Equation(2) in that the root-raised-cosine pulse h[t] is replaced with theraised-cosine pulse g[t].

[0375] The received signal that has been match-filtered to the chippulse is also match-filtered in the illustrated embodiment to the usercode sequence in order to obtain detection statistic, herein referred toas y_(k), for the k^(th) virtual user. Because there are K_(v) codes,there are K_(v) such detection statistics. For each virtual user, thedetection statistics can be collected into a column vector y[m] whosem^(th) entry corresponds to the m^(th) symbol period. More particularly,the matched filter output y_(l)[m] for the l^(th) virtual user can bewritten as: $\begin{matrix}{{y_{l}\lbrack m\rbrack} \equiv {{Re}\left\{ {\sum\limits_{q = 1}^{L}{{{\hat{a}}_{lq}^{*} \cdot \frac{1}{2N_{l}}}{\sum\limits_{n}{{r\left\lbrack {{nN}_{c} + {\hat{\tau}}_{lq} + {mT}} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}} \right\}}} & (4)\end{matrix}$

[0376] where â_(lq)* is an estimate of a_(lq)*, {circumflex over(τ)}_(lq) is an estimate of τ_(lq), N_(l) is the (non-zero) length ofcode c_(l)[n], and η_(l)[m] represents the match-filtered receivernoise. Substituting the expression for r[t] from Equation (3) inEquation (4) results in the following equation: $\begin{matrix}\begin{matrix}{{y_{l}\lbrack m\rbrack} \equiv {\sum\limits_{m^{\prime}}\sum\limits_{k = 1}^{K_{v}}}} \\{{{Re}\left\{ {\sum\limits_{q = 1}^{L}{{{\hat{a}}_{lq}^{*} \cdot \frac{1}{2N_{l}}}{\sum\limits_{n}{{{\overset{\sim}{s}}_{k}\left\lbrack {{nN}_{c} + {\hat{\tau}}_{lq} + {m^{\prime}\quad T}} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}} \right\}}} \\{{{b_{k}\left\lbrack {m - m^{\prime}} \right\rbrack} + {\eta_{l}\lbrack m\rbrack}}} \\{= {{\sum\limits_{m^{\prime}}{\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\left\lbrack m^{\prime} \right\rbrack}{b_{k}\left\lbrack {m - m^{\prime}} \right\rbrack}}}} + {\eta_{l}\lbrack m\rbrack}}} \\{{r_{lk}\left\lbrack m^{\prime} \right\rbrack} \equiv {{Re}\left\{ {\sum\limits_{q = 1}^{L}{{{\hat{a}}_{lq}^{*} \cdot \frac{1}{2N_{l}}}{\sum\limits_{n}{{{\overset{\sim}{s}}_{k}\left\lbrack {{nN}_{c} + {\hat{\tau}}_{lq} + {m^{\prime}\quad T}} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}} \right\}}} \\{= {\sum\limits_{q = 1}^{L}\sum\limits_{q^{\prime} = 1}^{L}}} \\{{{Re}\left\{ {{\hat{a}}_{lq}^{*}{a_{{kq}^{\prime}} \cdot \frac{1}{2N_{l}}}{\sum\limits_{n}{{s_{k}\left\lbrack {{nN}_{c} + {m^{\prime}\quad T} + {\hat{\tau}}_{lq} - \tau_{{kq}^{\prime}}} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}} \right\}}} \\{= {\sum\limits_{q = 1}^{L}\sum\limits_{q^{\prime} = 1}^{L}}} \\{{{Re}\left\{ {{\hat{a}}_{lq}^{*}{a_{{kq}^{\prime}} \cdot \frac{1}{2N_{l}}}{\sum\limits_{n}{\sum\limits_{p}{g\left\lbrack {{\left( {n - p} \right)N_{c}} + {m^{\prime}\quad T} +} \right.}}}} \right.}} \\\left. {{\left. {{\hat{\tau}}_{lq} - \tau_{{kq}^{\prime}}} \right\rbrack \cdot {c_{k}\lbrack p\rbrack}}{c_{l}^{*}\lbrack n\rbrack}} \right\}\end{matrix} & (5)\end{matrix}$

[0377] The terms for m′=0 result from asynchronous users.

[0378] Calculation of the R-Matrix

[0379] Determination of the R-matrix elements defined by Equation (5)above can be divided into two or more separate calculations, each havingan associated time constant or period of execution corresponding to atime constant or period during which a corresponding characteristic ofthe user waveforms are expected to change in real time. In theillustrated embodiment, three sets of calculations are employed asreflected in the following equations: $\begin{matrix}\begin{matrix}{{r_{lk}\left\lbrack m^{\prime} \right\rbrack} = {\sum\limits_{q = 1}^{L}\sum\limits_{q^{\prime} = 1}^{L}}} \\{{{Re}\left\{ {a_{lq}^{*}{a_{{kq}^{\prime}} \cdot \frac{1}{2N_{l}}}{\sum\limits_{n}{\sum\limits_{p}{g\left\lbrack {{\left( {n - p} \right)N_{c}} + {m^{\prime}\quad T} +} \right.}}}} \right.}} \\\left. {\left. {\tau_{lq} - \tau_{{kq}^{\prime}}} \right\rbrack {{c_{k}\lbrack p\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}} \right\} \\{= {\sum\limits_{q = 1}^{L}{\sum\limits_{q^{\prime} = 1}^{L}{{Re}\left\{ {a_{lq}^{*}{a_{{kq}^{\prime}} \cdot {C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack}}} \right\}}}}} \\{{C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{\sum\limits_{p}{g\left\lbrack {{\left( {n - p} \right)N_{c\quad}} + {m^{\prime}T} +} \right.}}}}} \\{\left. {\tau_{lq} - \tau_{{kq}^{\prime}}} \right\rbrack {{c_{k}\lbrack p\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{m}{g\left\lbrack {{mN}_{c} + {m^{\prime}T} + \tau_{lq} - \tau_{{kq}^{\prime}}} \right\rbrack}}}} \\{{\sum\limits_{n}{{c_{k}\left\lbrack {n - m} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{m}{{g\left\lbrack {{mN}_{c} + {m^{\prime}T} + \tau_{lq} - \tau_{{kq}^{\prime}}} \right\rbrack}{\Gamma_{lk}\lbrack m\rbrack}}}}} \\{{\Gamma_{lk}\lbrack m\rbrack} \equiv {\sum\limits_{n}{{c_{k}\left\lbrack {n - m} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}\end{matrix} & (6)\end{matrix}$

[0380] where the hats ({circumflex over ( )}), indicating parameterestimates, have been omitted.

[0381] With reference to Equation (6), the Γ-matrix, whose elements varywith the slowest time constant, represents the user code correlationsfor all values of offset m. For the case of 100 voice users, the totalmemory requirement for storing the Γ-matrix elements is 21 Mbytes basedon two bytes (e.g., the real and imaginary parts) per element. In theillustrated embodiment, the Γ-matrix matrix is updated only when newcodes associated with new users are added to the system. Hence, theΓ-matrix is effectively a quasi-static matrix, and thus, itscomputational requirements are minimal.

[0382] The selection of the most efficient method for calculating theΓ-matrix elements depends on the non-zero length of the codes. Forexample, the non-zero length of the codes in case of high data-rateusers can be only 4 chips long. In such a case, a direct convolution,e.g., convolution in the time domain, can be the most efficient methodof calculating the elements of the Γ-matrix. For low data-rate users, itmay be more efficient to calculate the elements of the Γ-matrix byutilizing Fast Fourier Transforms (FFTs) to perform convolutions in thefrequency domain.

[0383] In one method according to the teachings of the invention, theC-matrix elements are calculated by utilizing the Γ-matrix elements. TheC-matrix elements need to be calculated upon occurrence of a change in auser's delay lag (e.g., time-lag). For example, consider a case in whicheach multi-path component changes on average every 400 ms, and thelength of the g[ ] function is 48 samples. In such a case, assuming anover-sampling by four, then forty-eight operations per element need tobe performed (for example, 12 multiple accumulations, real x complex,for each element). Further, if 100 low-rate users (i.e., 200 virtualusers) are utilizing the system, and assuming a single multipath lag offour changes for one user, a total of (1.5)(2)K_(v)LN_(v) elements needto be calculated. The factor of 1.5 arises from the three C-matrices(e.g., m′=−1,0,1) which is reduced by a factor two as a result of aconjugate symmetry condition. Moreover, the factor two arises based onthe fact that both rows and columns need to be updated. The factor N_(v)represents the number of virtual users per physical user, which for thelowest rate users is N_(v)=2 as stated above. In total, this amounts toapproximately 230,400 operations per multipath component per physicaluser. Accordingly, it gives rise to 230 MOPS based on 100 physical userswith four multipath components per user, each changing once per 400msec. Of course, in other embodiments these values can differ.

[0384] The C-matrices are then utilized to calculate the R-matrices.More particularly, the elements of the R-matrix can be obtained asfollows by utilizing Equation (6) above: $\begin{matrix}\begin{matrix}{{r_{lk}\left\lbrack m^{\prime} \right\rbrack} = {\sum\limits_{q = 1}^{L}{\sum\limits_{q^{\prime} = 1}^{L}{{Re}\left\{ {{\hat{a}}_{lq}^{*}{a_{{kq}^{\prime}} \cdot {C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack}}} \right\}}}}} \\{= {{Re}\left\{ {a_{l}^{H} \cdot {C_{lk}\left\lbrack m^{\prime} \right\rbrack} \cdot a_{k}} \right\}}}\end{matrix} & (7)\end{matrix}$

[0385] where a_(k) are L×1 vectors, and C_(lk)[m′] are L×L matrices. Therate at which the above calculations need to be performed depends on thevelocity of the users. For example, in one embodiment, the update rateis selected to be 1.33 msec. An update rate that is too slow such thatthe estimated values of the R-matrix deviate significantly from theactual R-matrix values results in a degradation of the MUD efficiency.For example, FIG. 14 presents a graph that depicts the change in the MUDefficiency versus user velocity for an update rate of 1.33 msec, whichcorresponds to two WCDMA time slots. This graph indicates that the MUDefficiency is high for users having velocities that are less than about100 km/h. The graph further shows that the interference corresponding tofast users is not canceled as effectively as the interferencecorresponding to slow users. Thus, for a system that is utilized by amix of fast and slow users, the total MUD efficiency is an average ofthe MUD efficiency for the range of user velocities. Utilizing the aboveEquation (7), the R-matrix elements can be calculated in terms of an Xmatrix that represents amplitude-amplitude multiplies as shown below:

r _(lk) [m′]=Re{tr[a _(l) ^(H) ·C _(lk) [m′]·a _(k) ]}=Re{tr[C _(lk)[m′]·a _(k) ·a _(l) ^(H) ]}≡Re{tr[C _(lk) [m′]·X _(lk) ]}=tr[C _(lk)^(R) [m′]·X _(lk) ^(R) ]−tr[C _(lk) ^(l) [m′]·X _(lk) ^(l)]

X _(lk) ≡a _(k) ·a _(l) ^(ll) ≡X _(lk) ^(R) +jX _(lk) ^(l)

C _(lk) [m′]≡C _(lk) ^(R) [m′]+jC _(lk) ^(l) [m′]  (8)

[0386] The use of the X-matrix as illustrated above advantageouslyallows reusing the X-matrix multiplies for all virtual users associatedwith a physical user and for all m′ (i.e., m=0, 1). The remainingcalculations can be expressed as a single real dot product of length2L2=32. The calculations can be performed, for example, in 16-bit fixedpoint math. Then, the total operations can amount to1.5(4)(K_(v)L)2=3.84 MOPS resulting in a processing requirement of 2.90GOPS. The X-matrix multiplies, when amortized, amount to an additional0.7 GOPS. Thus, the total processing requirement can be 3.60 GOPS.

[0387] The matched-filter outputs can be obtained from the aboveEquation (5) as follows: $\begin{matrix}\begin{matrix}{{y_{l}\lbrack m\rbrack} = {{{r_{ll}\lbrack 0\rbrack}{b_{l}\lbrack m\rbrack}} + {\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\left\lbrack {- 1} \right\rbrack}{b_{k}\left\lbrack {m + 1} \right\rbrack}}} +}} \\{{{\sum\limits_{k = 1}^{K_{v}}{\left\lbrack {{r_{lk}\lbrack 0\rbrack} - {{r_{ll}\lbrack 0\rbrack}\delta_{lk}}} \right\rbrack {b_{k}\lbrack m\rbrack}}} +}} \\{{{\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\lbrack 1\rbrack}{b_{k}\left\lbrack {m - 1} \right\rbrack}}} + {\eta_{l}\lbrack m\rbrack}}}\end{matrix} & (9)\end{matrix}$

[0388] wherein the first term represents a signal of interest, and theremaining terms represent Multiple Access Interference (MAI) and noise.The illustrated embodiment uses a Multistate Decision Feedbackinterference Cancellation (MDFIC) algorithm can be utilized to solve forthe symbol estimates in accord with the following relationship:$\begin{matrix}\begin{matrix}{{{\hat{b}}_{l}\lbrack m\rbrack} = {{sign}\left\{ {{y_{l}\lbrack m\rbrack} - {\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\left\lbrack {- 1} \right\rbrack}{{\hat{b}}_{k}\left\lbrack {m + 1} \right\rbrack}}} -} \right.}} \\{{{\sum\limits_{k = 1}^{K_{v}}{\left\lbrack {{r_{lk}\lbrack 0\rbrack} - {{r_{ll}\lbrack 0\rbrack}\delta_{lk}}} \right\rbrack {{\hat{b}}_{k}\lbrack m\rbrack}}} -}} \\\left. {\sum\limits_{k = 1}^{K_{v}}{{r_{lk}\lbrack 1\rbrack}{{\hat{b}}_{k}\left\lbrack {m - 1} \right\rbrack}}} \right\}\end{matrix} & (10)\end{matrix}$

[0389] with initial estimates given by hard decisions on thematched-filter detection statistics,

{circumflex over (b)}_(l) [m]=sign{y _(l) [m]}.

[0390] A further appreciation of these and alternate MDFIC techniquesmay be attained by reference to An MDFIC technique which is described inan article by T. R. Giallorenzi and S. G. Wilson, titled, “Decisionfeedback multi-user receivers for asynchronous CDMA systems”, publishedin IEEE Global Telecommunications Conference, pages 1677-1682 (June1993), and herein incorporated by reference. Related techniques, knownas, is closely related to Successive Interference Cancellation (SIC) andParallel Interference Cancellation (PIC), can be used in addition orinstead.

[0391] In the illustrated embodiment, the new estimates {circumflex over(b)}_(l)[m] are immediately introduced back into the interferencecancellation as they are calculated. Hence at any given cancellationstep, the best available symbol estimates are used. In one embodiment,the above iteration can be performed on a block of 20 symbols, whichrepresents two WCDMA time slots. The R-matrices are assumed to beconstant over this period. The sign detector in Equation (10) above canbe replaced by a hyperbolic tangent detector to improve performanceunder high input BER. A hyperbolic tangent detector has a single slopeparameter which varies from one iteration to another.

[0392] The three R-matrices (R[−1], R[0] and R[1]) are each K_(v)xK_(v)in size. Hence, the total number of operation per iteration is 6K_(v) ².The computational complexity of the MDFIC algorithm depends on the totalnumber of virtual users, which in turn depends on the mix of users atvarious spreading factors. For K_(v)=200 users (e.g. 100 low-rateusers), the computation requires 240,000 operations. In one embodiment,two iterations are employed which require a total of 480,000 operations.For real-time applications, these operations must be performed in{fraction (1/15)} ms or less. Thus, the total processing requirement is7.2 GOPS. Computational complexity is markedly reduced if a thresholdparameter is set such that IC is performed only for those |y_(l)[m]|below the threshold. If |y_(l)[m]| is large, there is little doubt as tothe sign of b_(l)[m], and IC need not be performed. The value of thethreshold parameter can be variable from stage to stage.

[0393] C-Matrix Calculation

[0394] As discussed above, the C-matrix elements are utilized tocalculate the R-matrices, which in turn are employed by an MDFInterference Cancellation routine. The C-matrix elements can becalculated by utilizing different techniques, as described elsewhereherein. In one approach, the C-matrix elements are calculated directlywhereas in another approach the C-matrix elements are computed from theΓ-matrix elements, as discussed in detail below and illustratedelsewhere herein.

[0395] More particularly, in one method for calculating the C matrixelements, each C-matrix element can be calculated as a dot productbetween the kth user's waveform and the lth user's code stream, eachoffset by some multipath delay. For this method of calculation, eachtime a user's multipath profile changes, all the C-matrix elementsassociated with the changed profile need to be recalculated. A user'sprofile can change very rapidly, for example, every 100 msec or faster,thereby necessitating frequent updates of the C-matrix elements. Suchfrequent updates of the C-matrix elements can give rise to a largeamount of overhead associated with computations that need to beperformed before obtaining each dot product. In fact, obtaining theC-matrix elements by the above approach may require dedicating an entireprocessor for performing the requisite calculations.

[0396] Another approach according to the teachings of the invention forcalculating the C-matrix elements pre-calculates the code correlationsup-front when a user is added to the system. The calculations areperformed over all possible code offsets and can be stored, for example,in a large array (e.g., approximately 21 Mbytes in size), hereinreferred to as the Γ-matrix. This allows updating C-matrix elements whena user's profile changes by extracting the appropriate elements from theGamma matrix and performing minor calculations. Since the Γ-matrixelements are calculated for all code offsets, FFT can be effectivelyemployed to speed up the calculations. Further, because all code offsetsare pre-calculated, rapidly changing multipath profiles can be readilyaccommodated. This approach has a further advantage in that it minimizesthe use of resources that need to be allocated for extracting theC-matrix elements when the number of users accessing system is constant.

[0397] C-Matrix Elements Expressed in Terms of Code Correlations

[0398] As discussed above, the R-matrix elements can be given in termsof the C-matrix elements as follows: $\begin{matrix}\begin{matrix}{{{{\hat{\rho}}_{lk}\left\lbrack m^{\prime} \right\rbrack}A_{l}A_{k}} = {\sum\limits_{q = 1}^{L}{\sum\limits_{q^{\prime} = 1}^{L}{{Re}\left\{ {{\hat{a}}_{lq}^{*}{{\hat{a}}_{{kq}^{\prime}} \cdot {C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack}}} \right\}}}}} \\{{C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{s_{k}\left\lbrack {{nN}_{c} + {m^{\prime}T} + {\hat{\tau}}_{lq} - {\hat{\tau}}_{{kq}^{\prime}}} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}}\end{matrix} & (11)\end{matrix}$

[0399] where C_(lkqq′)[m′] is a five-dimensional matrix of codecorrelations. Both l and k range from 1 to K_(v), where K_(v) is thenumber of virtual users. The indices q and q′ range from 1 to L,representing the number of multipath components, which in this exemplaryembodiment is assumed to be 4. The symbol period offset m′ ranges from−1 to 1. The total number of matrix elements to be calculated is thenN_(c)=3(K_(v)L)²=3(800)²=1.92M complex elements, requiring 3.84 MB ofstorage if each element is a byte. The following symmetry property ofthe C-matrix elements can be utilized to halve the storage requirement,for example, in this case to 1.92 MB: $\begin{matrix}{{C_{{klq}^{\prime}\quad q}\left\lbrack {- m^{\prime}} \right\rbrack} = {\frac{N_{l}}{N_{k}}{C_{{lkqq}^{\prime}}^{*}\left\lbrack m^{\prime} \right\rbrack}}} & (12)\end{matrix}$

[0400] It is evident from the above Equation (12) that each element ofC_(lkqq′)[m′] is formed as a complex dot product between a code vectorc_(l) and a waveform vector s_(kqq′). In this exemplary embodiment, thelength of the code vector is 256. The waveform s_(k)[t], herein referredto as the signature waveform for the kth virtual user, is generated byapplying a pulse-shaping filter g[t] to the spread code sequencec_(k)[n] as follows: $\begin{matrix}{{s_{k}\lbrack t\rbrack} = {\sum\limits_{p = 0}^{N - 1}{{g\left\lbrack {t - {pN}_{c}} \right\rbrack}{c_{k}\lbrack p\rbrack}}}} & (13)\end{matrix}$

[0401] where N=256 and g[t] is the raised-cosine pulse shape. Since g[t]is a raised-cosine pulse as opposed to a root-raised-cosine pulse, thesignature waveform s_(k)[t] includes the effects of filtering by thematched chip filter. For spreading factors less than 256, some of thechips c_(k)[p] are zero. The length of the waveform vector s_(k)[t] isL_(g)+255N_(c), where L_(g) is the length of the raised-cosine pulsevector g[t] and N_(c) is the number of samples per chip. The values forthese parameters in this exemplary embodiment are selected to beL_(g)=48 and N_(c)=4. The length of the waveform vector is then 1068,but for performing the dot product, it is accessed at a stride ofN_(c)=4, which results in an effective length of 267.

[0402] In this exemplary embodiment, the raised-cosine pulse vector g[t]is defined to be non-zero from t=−L_(g)/2+1:L_(g)/2, with g|0|=1. Withthis definition the waveform s_(k)[t] is non-zero in a range fromt=−L_(g)/2+1:L_(g)/2+255N_(c).

[0403] By combining Equations (11) and (13), the calculation of theC-matrix elements can be expressed directly in terms of the user codecorrelations. These correlations can be calculated up front and stored,for example, in SDRAM. The C-matrix elements expressed in terms of thecode correlations Γ_(lk)[m] are: $\begin{matrix}\begin{matrix}{{C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{s_{k}\left\lbrack {{nN}_{c} + {m^{\prime}T} + {\hat{\tau}}_{lq} - {\hat{\tau}}_{{kq}^{\prime}}} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}{\sum\limits_{p}{g\left\lbrack {{\left( {n - p} \right)N_{c\quad}} + {m^{\prime}T} +} \right.}}}}} \\{{\left. {{\hat{\tau}}_{lq} - {\hat{\tau}}_{{kq}^{\prime}}} \right\rbrack} \cdot {c_{k}\lbrack p\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}{\sum\limits_{m}{{g\left\lbrack {{mN}_{c} + \tau} \right\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}}} \\{= {\sum\limits_{m}{{{g\left\lbrack {{mN}_{c} + \tau} \right\rbrack} \cdot \frac{1}{2N_{l}}}{\sum\limits_{n}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}}} \\{= {\sum\limits_{m}{{g\left\lbrack {{mN}_{c} + \tau} \right\rbrack} \cdot {\Gamma_{lk}\lbrack m\rbrack}}}} \\{{\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}} \\{\tau \equiv {{m^{\prime}T} + {\hat{\tau}}_{lq} - {\hat{\tau}}_{{kq}^{\prime}}}}\end{matrix} & (14)\end{matrix}$

[0404] Since the pulse shape vector g[n] is of length L_(g). at most2L_(g)/N_(c)=24 real macs need to be performed to calculate each elementC_(lkqq′)[m′] (the factor of 2 arises because the code correlationsΓ_(lk)[m] are complex). For a given τ, the method of the inventionefficiently calculates the range of m values for which g[mN_(c)+τ] isnon-zero as described below. The minimum value of m is given bym_(min1)N_(c)+τ=−L_(g)/2+1, and τ is given by τ=m′NN_(c)+τ_(lq)−τ_(kq′).If each τ value is decomposed as τ_(lq)=n_(lq)N_(c)+p_(lq), thenm_(min1)=ceil[(−τ−L_(g)/2+1)/N_(c)]=−m′N−n_(lq)+n_(kq′)−L_(g)/(2N_(c))+ceil[(p_(kq′)−p_(lq)+1)/N_(c)],where ceil[(p_(kq′)−p_(lq)+1)/N_(c)] will be either 0 or 1. It isconvenient to set this value to 0. In order to avoid accessing valuesoutside the allocation for g[n], g[n]=0.0 forn=−L_(g)/2:−L_(g)/2−(N_(c)−1). All but one of the N_(c) ² possiblevalues for ceil[(p_(kq′)−p_(lq)+1)/N_(c)] are 0.

[0405] Accordingly, the following relation holds:

m _(min1) =−m′N−n _(lq) +n _(kq′) −L _(g)/(2N _(c))  (15)

[0406] wherein L_(R) is divisible by 2N_(c), and L_(g)/(2N_(c)) is asystem constant.

[0407] Since, the maximum value of m is given bym_(max1)N_(c)+τ=L_(g)/2, the following holds:

m _(max1)=floor[(−τ+L _(g)/2)/N _(c) ]=−m′N−n _(lq) +n _(kq′) +L_(g)/(2N _(c))+floor[(p _(kq′) p _(lq))/N _(c)].

[0408] Further, floor[(p_(kq′)−p_(lq))/N_(c)] can be either −1 or 0. Inthis exemplary embodiment, it is convenient to set this value to 0. Inorder to avoid accessing values outside the allocation for g[n], g[n] isset to 0.0 (g[n]=0.0) for n=−L_(g)/2+1:L_(g)/2+N_(c). It is noted thathalf of the N_(c) ² possible values for floor[(p_(kq′)−p_(lq))/N_(c)]are 0. Accordingly, the following relation holds:

m _(max1) =−m′N−n _(lq) +n _(kq′) +L _(g)/(2N _(c))  (16)

[0409] The values of m_(min1) and m_(max1) are quickly calculable.

[0410] The calculation of the C-matrix elements typically requires asmall subset of the Γ matrix elements. The Γ matrix elements can becalculated for all values of m by utilizing Fast Fourier Transform (FFT)as described in detail below.

[0411] Using FFT to Calculate the Γ-Matrix Elements

[0412] It was shown above that the Γ-matrix elements can be representedas a convolution. Accordingly, the FFT convolution theorem can beexploited to calculate the Γ-matrix elements. From the above Equation(14), the Γ-matrix elements are defined as follows: $\begin{matrix}{{\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n = 0}^{N - 1}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}} & (17)\end{matrix}$

[0413] where N=256. Three streams are related by this equation. In orderto apply the convolution theorem, these three streams are defined overthe same time interval. The code streams c_(k)[n] and c_(l)[n] arenon-zero from n=0:255. These intervals are based on the maximumspreading factor. For higher data-rate users, the intervals over whichthe streams are non-zero are reduced further. The intervals derived fromthe highest spreading factor are of particular interest in defining acommon interval for all streams because they represent the largestintervals. The common interval allows the FFTs to be reused for all userinteractions.

[0414] With reference to FIG. 15, the range of values of m for whichΓ_(lk)[m] is non-zero can be derived from the above intervals. Themaximum value of m is limited by n−m≧0, which gives

255−m _(max)=0z,900 m _(max)=255  (18)

[0415] and the minimum value of m is limited by n−m≧255, which gives

0−m _(min)=255

m _(min)=−255  (19)

[0416] To achieve a common interval for all three streams, an intervaldefined by m=−M/2: M/2−1, M=512 is selected. The streams are zero-paddedto fill up the interval, if needed.

[0417] Accordingly, the DFT and IDFT of the streams are given by thefollowing relations: $\begin{matrix}{{{C_{l}\lbrack r\rbrack} = {\sum\limits_{n = {- \frac{M}{2}}}^{\frac{M}{2} - 1}{{c_{l}\lbrack n\rbrack} \cdot ^{{- {j2\pi}}\quad {{nr}/M}}}}}{{c_{l}\lbrack r\rbrack} = {\frac{1}{M}{\sum\limits_{r = {- \frac{M}{2}}}^{\frac{M}{2} - 1}{{C_{l}\lbrack r\rbrack} \cdot ^{{j2\pi}\quad {{nr}/M}}}}}}} & (20)\end{matrix}$

[0418] which gives $\begin{matrix}\begin{matrix}{{\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n = {- \frac{M}{2}}}^{\frac{M}{2} - 1}{{c_{k}\left\lbrack {n - m} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}} \\{= {\frac{1}{2N_{l}M^{2}}{\sum\limits_{n = {- \frac{M}{2}}}^{\frac{M}{2} - 1}{\sum\limits_{i = {- \frac{M}{2}}}^{\frac{M}{2} - 1}{{C_{k}\lbrack r\rbrack} \cdot ^{{{j2\pi}{({n - m})}}{r/M}}}}}}} \\{{\sum\limits_{r^{\prime} = {- \frac{M}{2}}}^{\frac{M}{2} - 1}{{C_{l}^{*}\left\lbrack r^{\prime} \right\rbrack} \cdot ^{{- j}\quad 2\quad \pi \quad n\quad {r/M}}}}} \\{= {\frac{1}{2N_{l}M^{2}}{\sum\limits_{r = {- \frac{M}{2}}}^{\frac{M}{2} - 1}{{{C_{k}\lbrack r\rbrack} \cdot ^{{- {j2\pi}}\quad {{mr}/M}}}{\sum\limits_{r^{\prime} = {- \frac{M}{2}}}^{\frac{M}{2} - 1}{C_{l}^{*}\left\lbrack r^{\prime} \right\rbrack}}}}}} \\{{\sum\limits_{n = {- \frac{M}{2}}}^{\frac{M}{2} - 1}^{{j2\pi}\quad {{n{({r - r})}}/M}}}} \\{= {\frac{1}{2N_{l}M}{\sum\limits_{i = {- \frac{M}{2}}}^{\frac{M}{2} - 1}{{{C_{k}\lbrack r\rbrack} \cdot {C_{l}^{*}\lbrack r\rbrack}}^{{- j}\quad 2\quad \pi \quad {{mr}/M}}}}}}\end{matrix} & (21)\end{matrix}$

[0419] Hence, Γ_(lk)[m] can be calculated for all values of m byutilizing FFT. Based on the analysis presented above, many of thesevalues will be zero for high data rate users. In this exemplaryembodiment, only the non-zero values are stored in order to conservestorage space. The values of m for which Γ_(lk)[m] is non-zero can bedetermined analytically, as described in more detail below andillustrated elsewhere herein.

[0420] Storage and Retrieval of Γ-Matrix Elements

[0421] As discussed above, the values of the Γ-matrix elements which arenon-zero need to be determined for efficient storage of the Γ-matrix.For high data rate users, certain elements c_(l)[n] are zero, evenwithin the interval n=0:N−1, N=256. These zero values reduce theinterval over which Γ_(lk)[m] is non-zero. In order to determine theinterval for non-zero values consider the following relations:$\begin{matrix}{{\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n = 0}^{N - 1}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}} & (22)\end{matrix}$

[0422] The index j_(l) for the lth virtual user is defined such thatc_(l)[n] is non-zero only over the intervaln=j_(l)N_(l):j_(l)N_(l)+N_(l)−1. Correspondingly, the vector c_(k)[n] isnon-zero only over the interval n=j_(k)N_(k):j_(k)N_(k)+N_(k)−1. Giventhese definitions, Γ_(lk)[m] can be rewritten as $\begin{matrix}{{\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n = 0}^{N_{l} - 1}{{c_{l}^{*}\left\lbrack {n + {j_{l}N_{l}}} \right\rbrack} \cdot {c_{k}\left\lbrack {n + {j_{l}N_{l}} - m} \right\rbrack}}}}} & (23)\end{matrix}$

[0423] The minimum value of m for which Γ_(lk)[m] is non-zero is

m _(min2) =−j _(k) N _(k) +j _(l) N _(l) −N _(k)+1  (24)

[0424] and the maximum value of m for which Γ_(lk)[m] is non-zero is

m _(max2) =N _(l)−1−j _(k) N _(k) +j _(l) N _(l)  (25)

[0425] The total number of non-zero elements is then $\begin{matrix}\begin{matrix}{m_{total} \equiv {m_{max2} - m_{min2} + 1}} \\{= {N_{l} + N_{k} - 1}}\end{matrix} & (26)\end{matrix}$

[0426] The table below provides the number of bytes per l,k virtual-userpair based on 2 bytes per element—one byte for the real part and onebyte for the imaginary part. N_(k) = 256 728 64 32 16 8 4 N₁ = 256 1022766 638 574 542 526 518 128 766 510 382 318 286 270 262 64 638 382 254190 158 142 134 32 574 318 190 126 94 78 70 16 542 286 158 94 62 46 38 8526 270 142 78 46 30 22 4 518 262 134 70 38 22 14

[0427] The memory requirements for storing the Γ matrix for a givennumber of users at each spreading factor can be determined as describedbelow. For example, for K_(q) virtual users at spreading factorN_(q)≡2^(8−q), q=0:6, where K_(q) is the qth element of the vector K(some elements of K may be zero), the storage requirement can becomputed as follows. Let Table 1 above be stored in matrix M withelements M_(qq′). For example, M₀₀=1022, and M₀₁=766. The total memoryrequired by the Γ matrix in bytes is then given by the followingrelation $\begin{matrix}\begin{matrix}{M_{bytes} = {\sum\limits_{q = 0}^{6}\left\{ {{\frac{K_{q}\left( {K_{q} + 1} \right)}{2}M_{qq}} + {\sum\limits_{q^{\prime} = {q + 1}}^{6}{K_{q}K_{q^{\prime}}M_{{qq}^{\prime}}}}} \right\}}} \\{= {\frac{1}{2}{\sum\limits_{q = 0}^{6}\left\{ {{K_{q}M_{qq}} + {\sum\limits_{q^{\prime} = 0}^{6}{K_{q}K_{q^{\prime}}M_{{qq}^{\prime}}}}} \right\}}}}\end{matrix} & (27)\end{matrix}$

[0428] For example, for 200 virtual users at spreading factor N₀=256,K_(q)=200δ_(q0), which in turn results inM_(bytes)=½K₀(K₀+1)M₀₀=100(201)(1022)=20.5 MB. For 10 384 Kbps usersK_(q)=K₀δ_(q0)+K₆δ_(q6) with K₀=10 and K₆=640, which results in astorage requirement that is given by the following relations:

M _(bytes)=½K ₀(K ₀+1)M ₀₀ +K ₀ K ₆ M ₀₆+½K ₆(K ₆+1)M₆₆=5(11)(1022)+10(640)(518)+320(641)(14)=6.2 MB.

[0429] The Γ-matrix data can be addressed, stored, and accessed asdescribed below. In particular, for each pair (l,k), k>=l, there are 1complex Γ_(lk)[m] values for each value of m, where m ranges fromm_(min2) to m_(max2), and the total number of non-zero elements ism_(total)=m_(max2)−m_(min2)+1. Hence, for each pair (l,k), k>=l, thereexists 2m_(total) time-contiguous bytes.

[0430] In one embodiment, an array structure is created to access thedata, as shown below: struct { int m_min2; int m_max2; int m total;char * Glk; } G_info[N_VU_MAX][N_VU_MAX];

[0431] The C-matrix data can then be retrieved by utilizing thefollowing exemplary algorithm: m_(min2)=G_info[l][k].m_min2m_(max2)=G_info[l][k].m_max2 N_(g)=L_(g)/N_(c) Nl=m'*N−L_(g)/(2N_(c))for m'=0:1 for q=0:L−1 for q'=0:L−1 τ=m'T+τ_(lq)−τ_(kq')m_(min1)=N1−n_(lq)+n_(kq') m_(max1)=m_(min1)+N_(g) m_(min)=max[m_(min1),m_(min2)] m_(max)=min[m_(min1), m_(min2)] if m_(max)>=m_(min)m_(span)=m_(max)−m_(min)+1 sum1=0.0; ptr1=&G_info[1][k].Glk[m_(min)]ptr2=&g[m_(min)*N_(c)+τ] while m_(span)>0 sum1+=(*ptrl++)*(*ptr2++)m_(span)− end C[m'][l][k][q][q']=sum1 end end end end

[0432] Another method for calculating the Γ-matrix elements, hereinreferred to as the direct method, performs a direct convolution, forexample, by employing the SALzconvx function, to compute these elements.This direct method is preferable when the vector lengths are small. Asan illustration of the time required for performing calculations, Thetable below provides exemplary timing data based on a 400 MHz PPC7400with 16 MHz, 2 MB L2 cache, wherein the data is assumed to be residentin L1 cache. The performance loss for L2 cache resident data is notsevere. M_(total) N_(l) Timing (μs) GFLOPS 1024 4 19.33 1.70 1024 829.73 2.20 1024 16 50.55 2.59 1024 32 92.32 2.84 1024 64 176.53 2.971024 128 346.80 3.47

[0433] As discussed above, FFT can also be utilized for calculating theΓ-matrix elements. The time required to perform a 512 complex FFT, within-place calculation, on a 400 MHz PPC7400 with 16 MHz, 2 MB L2 cache is10.94 μs for L1 resident data. Prior to performing the final FFT, acomplex vector multiplication of length 512 needs to be performed.Exemplary timings for this computation are provided in the followingtable: Length Location Timing (μs) GFLOPS 1024 L1 4.46 1.38 1024 L224.27 0.253 1024 DRAM 61.49 0.100

[0434] Further, exemplary timing data for moving data between memory andthe processor is provided in the following table: Length Location Timing(μs) 1024 L1 1.20 1024 L2 15.34 1024 DRAM 30.05

[0435]FIG. 16 illustrates the Γ-matrix elements that need to becalculated when a new physical user is added to the system. Addition ofa new physical user to the system results in adding 1+J virtual users tothe systems: that is, 1 control channel+J=256/SF data channels. Thenumber K_(v) represents the number of initial virtual users. Hence thereare (K_(v)+1) elements added to the Γ-matrix as a result of increase inthe number of the control channels, and J(K_(v)+1)+J(J+1)/2 elementsadded as a result of increase in the number of the data channels. Thetotal number of elements added is then (J+1)[K_(v)+1+J/2]. If FFT isutilized to perform the calculations, the total number of FFTs to beperformed is (J+1)+(J+1)[K_(v)+1+J/2]. The first term represents theFFTs to transform c_(k)[n], and the second term represents the(J+1)[K_(v)+1+J/2] inverse FFTs of FFT{c_(k)[n]}*FFT{c_(l)*[n]}. Thetime to perform the complex 512 FFTs can be, for example, 10.94 μs,whereas the time to perform the complex vector multiply and the complex512 FFT can be, for example, 24.27/2+10.94=23.08 μs.

[0436] In order to provide illustrative examples of processing times,two cases of interest are considered below. In the first case scenario,a voice user is added to the system while K=100 users (K_(v)=200 virtualusers) are accessing the system. Not all of these users are active. Thecontrol channels are always active, but the data channels have activityfactor AF=0.4. The mean number of active virtual users is thenK+AF*K=140. The standard deviation is σ={square root}{square root over(K·AF·(1−AF))}=4.90. Accordingly, there are K_(v)<140+3σ<155 active userwith a high probability.

[0437] The second case, which represents a more demanding scenario,arises when a single 384 Kbps data user is added while a number of usersare accessing the system. A single 384 Kbps data user adds interferenceequal to (0.25+0.125* 100)/(0.25+0.400*1)˜=20 voice users. Hence, thenumber of voice users accessing the system must be reduced toapproximately K=100−20=80(K_(v)=160). The 3σ number of active virtualusers is then 80+(0.125)80+3(3.0)=99 active virtual users. The reasonthis scenario is more demanding is that when a single 384 Kbps data useris added to the system, J+1=64+1=65 virtual users are added to thesystem.

[0438] In the first case scenario in which there are K_(v)=200 virtualusers accessing the system and a voice user is added to the system(J=1), the total time to add the voice user can be (1+1)(10.94μs)+(1+1)[200+1+½](23.08 μs)=9.3 ms.

[0439] For the second scenario in which there are K_(v)=160 virtualusers accessing the system and a 384 Kbps data user is added (J=64), thetotal time to add the 384 Kbps user can be (64+1)(10.94μs)+(64+1)[160+1+64/2](23.08 μs)=290 ms, which is significantly largerthan 9.3 ms. Hence, at least for high data-rate user, the Γ-matrixelements are calculated via convolutions.

[0440] In the direct method of calculating the Γ-matrix elements, theSAL zconvx function is utilized to perform the following convolution:$\begin{matrix}\begin{matrix}{{\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n = 0}^{N_{l} - 1}{{c_{l}^{*}\left\lbrack {n + {j_{l}N_{l}}} \right\rbrack} \cdot {c_{k}\left\lbrack {n + {j_{l}N_{l}} - m} \right\rbrack}}}}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n = 0}^{N_{k} - 1}{{c_{l}^{*}\left\lbrack {n + {j_{k}N_{k}} + m} \right\rbrack} \cdot {{c_{k}\left\lbrack {n + {j_{k}N_{k}}} \right\rbrack}.}}}}}\end{matrix} & (28)\end{matrix}$

[0441] For each value of m, N_(min)=min{N_(l), N_(k)} complex macs(cmacs) need to be performed. Each cmac requires 8 flops, and there arem_(total)=N_(l)+N_(k)31 1 m-values to calculate. Hence, the total numberof flops is 8N_(min)(N_(l)+N_(k)−1). In the following, it is assumedthat the convolution calculation is performed at 1.50 GOPs=1500 ops/μs.The time required to perform the convolutions is presented in the tablebelow N_(k) = 256 728 64 32 16 8 4 N₁ = 256 697.69 261.46 108.89 48.9823.13 11.22 5.53 128 261.46 174.08 65.19 27.14 12.20 5.76 2.79 64 108.8965.19 43.35 16.21 6.74 3.03 1.43 32 48.98 27.14 16.21 10.75 4.01 1.660.75 16 23.13 12.20 6.74 4.01 2.65 0.98 0.41 8 11.22 5.76 3.03 1.66 0.980.64 0.23 4 5.53 2.79 1.43 0.75 0.41 0.23 0.15

[0442] The total time to calculate the Γ-matrix is then given by thefollowing relation: $\begin{matrix}\begin{matrix}{{T_{\Gamma}(K)} = {\sum\limits_{q = 0}^{6}\left\{ {{\frac{K_{q}\left( {K_{q} + 1} \right)}{2}T_{qq}} + {\sum\limits_{q^{\prime} = {q + 1}}^{6}{K_{q}K_{q^{\prime}}T_{{qq}^{\prime}}}}} \right\}}} \\{= {\frac{1}{2}{\sum\limits_{q = 0}^{6}\left\{ {{K_{q}T_{qq}} + {\sum\limits_{q^{\prime} = 0}^{6}{K_{q}K_{q^{\prime}}T_{{qq}^{\prime}}}}} \right\}}}} \\{= {\frac{1}{2}\left\lbrack {{K \cdot {{diag}(T)}} + {K^{T} \cdot T \cdot K}} \right\rbrack}}\end{matrix} & (29)\end{matrix}$

[0443] where T_(qq) are the elements in the above Table 5. Now supposeK′=K+Δ, where Δ_(q)=J_(x)δ_(qx)+J_(y)δ_(qy), and where x and y are notequal. Then $\begin{matrix}\begin{matrix}{{\Delta \quad T_{\Gamma}} \equiv {{T_{\Gamma}\left( K^{\prime} \right)} - {T_{\Gamma}(K)}}} \\{= {{\frac{1}{2}{J_{x}\left( {J_{x} + 1} \right)}T_{xx}} + {\frac{1}{2}{J_{y}\left( {J_{y} + 1} \right)}T_{yy}} +}} \\{{{J_{x}J_{y}T_{xy}} + {\sum\limits_{q = 0}^{6}{K_{q}\left\{ {{J_{x}T_{xq}} + {J_{y}T_{yq}}} \right\}}}}}\end{matrix} & (30)\end{matrix}$

[0444] In the first scenario, there are K_(v)=200 virtual usersaccessing the system and a voice user is added to the system (J=1).Hence, K_(q)=K_(v)δ_(q0)(SF=256), K_(v)=200, J_(x)=J=2 and J_(y)=0. Thetotal time is then

½J(J+1)T₀₀ +JK _(v) T ₀₀=(0.5)(2)(3)(0.70 ms)+(2)(200)(0.70 ms)=283 ms

[0445] This number is large enough to require that for voice users, atleast, the Γ-matrix elementst be calculated via FFTs.

[0446] For the second scenario, there are K_(v)=160 virtual usersaccessing the system and a 384 Kbps data user is added to the system(J=64). Hence, K_(q)=K_(v)δ_(q0)(SF=256), K_(v)=160, J_(x)=1 (control)and J_(y)=J=64 (data). The total time is then

[0447] (K_(v)+1)T₀₀+J(K_(v)+1)T₀₆+(J+1)(J/2)T₆₆=(161)(697.7μs)+(64)(161)(5.53 μs)+(65)(32)(0.15 μs)=112.33 ms+56.98 ms+0.31ms=169.62 ms

[0448] Accordingly, these calculations should also be performed byutilizing FFT, which can require, for example, 23.08 μs per convolution.In addition, 1 FFT is required to compute FFT{c_(k)*[n]}) for the singlecontrol channel. This can require an additional 10.94 μs. The totaltime, then, to add the 384 Kbps user is

[0449] 10.94 μs+(161)(23.08)μs+(64)(161)(5.53)μs+(65)(32)(0.15)μs==61.02mst

[0450] Γ-Matrix Elements to SDRAM

[0451] With reference to above Equation (27), the size of the Γ-matrixin bytes is given by the following relation: $\begin{matrix}\begin{matrix}{{M_{b}(K)} = {\sum\limits_{q = 0}^{6}\left\{ {{\frac{K_{q}\left( {K_{q} + 1} \right)}{2}M_{qq}} + {\sum\limits_{q^{\prime} = {q + 1}}^{6}{K_{q}K_{q^{\prime}}M_{{qq}^{\prime}}}}} \right\}}} \\{= {\frac{1}{2}{\sum\limits_{q = 0}^{6}\left\{ {{K_{q}M_{qq}} + {\sum\limits_{q^{\prime} = 0}^{6}{K_{q}K_{q^{\prime}}M_{{qq}^{\prime}}}}} \right\}}}} \\{= {\frac{1}{2}\left\lbrack {{K \cdot {{diag}(M)}} + {K^{T} \cdot M \cdot K}} \right\rbrack}}\end{matrix} & (31)\end{matrix}$

[0452] Now suppose K′=K+Δ, where Δ_(q)=J_(x)δ_(qx)+J_(y)δ_(qy), andwhere x and y are not equal. Then $\begin{matrix}\begin{matrix}{{\Delta \quad M_{b}} \equiv {{M_{b}\left( K^{\prime} \right)} - {M_{b}(K)}}} \\{= {{\frac{1}{2}{J_{x}\left( {J_{x} + 1} \right)}M_{xx}} + {\frac{1}{2}{J_{y}\left( {J_{y} + 1} \right)}M_{yy}} + J +}} \\{{\sum\limits_{q = 0}^{6}{K_{q}\left\{ {{J_{x}M_{xq}} + {J_{y}M_{yq}}} \right\}}}}\end{matrix} & (32)\end{matrix}$

[0453] Consider a first exemplary scenario in whichK_(q)=200δ_(q0)(SF=256) and a single voice user is added to the system:J_(x)=2 (data plus control), and J_(y)=0. The total number of bytes tobe written to SDRAM is then 0.5(2)(3)(1022)+200(2)(1022)=0.412 MB.Assuming a SDRAM write speed of 133 MHz*8 bytes*0.5=532 MB/s, the timerequired to write Γ-matrix to SDRAM is then 0.774 ms.

[0454] For additional illustration of the time required for storing theΓ-matrix, consider a second scenario in which K_(q)=160δ_(q0)(SF=256),and a single 384 Kbps (SF=4) user is added to the system: J_(x)=1(control) and J_(y)=64 (data). The total number of bytes is then0.5(1)(2)(1022)+0.5(64)(65)(14)+160{1(1022)+64(518)}=5.498 MB. The SDRAMwrite speed is 133 MHz*8 bytes*0.5=532 MB/s. The time to write to SDRAMis then 10.33 ms.

[0455] Packing the Gamma-Matrix Elements in SDRAM

[0456] In this exemplary embodiment, the maximum total size of theΓ-matrix is 20.5 MB. If it is assumed that in order to pack the matrix,every element must be moved (this is the most demanding scenario), thenfor a SDRAM speed of 133 MHz*8 bytes*0.5=532 MB/s, the move time is then2(20.5 MB)/(532 MB/s)=77.1 ms. If the Γ-matrix is divided over threeprocessors, this time is reduced by a factor of 3. The packing can bedone incrementally, so there is no strict time limit.

[0457] Extracting Gamma-Matrix Elements from SDRAM

[0458] As described above, in this exemplary embodiment, the C-matrixdata is retrieved by utilizing the following algorithm:m_(min2)=G_info[l][k].m_min2 m_(max2)=G_info[l][k].m_max2N_(g)=L_(g)/N_(c) Nl=m'*N−L_(g)/(2N_(c)) for m'=0:1 for q=0:L−1 forq'=0:L−1 τ=m'T+τ_(lq)−τ_(kq') m_(min1)=N1−n_(lq)+n_(kq')m_(max1)=m_(min1)+N_(g) m_(min)=max[m_(min1), m_(min2)]m_(max)=min[m_(min1), m_(min2)] if m_(max)>=m_(min)m_(span)=m_(max)−m_(min)+1 sum1=0.0; ptr1=&G_info[1][k].Glk[m_(min)]ptr2=&g[m_(min)*N_(c)+τ] while m_(span)>0 sum1+=(*ptrl++)*(*ptr2++)m_(span)− end C[m'][l][k][q][q']=sum1 end end end end

[0459] The time requirements for calculating the Γ-matrix elements inthis exemplary embodiment, when a new user is added to the system wasdiscussed above. The time requirements for extracting the correspondingC-matrix elements are discussed below.

[0460] The Γ_(lk)[m] elements are accessed from SDRAM. It is highlylikely that these values will not be contained in either L1 or L2 cache.For a given (l,k) pair, however, the spread in τ is likely to be, formost cases, less than 8 μs (i.e. for a 4 μs delay spread), which equatesto (8 μs)(4 chips/μs)(2 bytes/chip)=64 bytes, or 2 cache lines. In anembodiment in which data is read in for two values of m′, a total of 4cache lines must be read. This will require 16 clocks, or about16/133=0.12 μs. However, in some embodiments, accesses to SDRAM may beperformed at about 50% efficiency so that the required time is about0.24 μs.

[0461] If a user l=x is added to the system, the elementsC[m′][x][k][q][q′] for all m′, k, q and q′ need to be fetched. Asindicated above, all the m′, q and q′ values are typically contained in4 cache lines. Hence, if there are K_(v) virtual users, 4K_(v) cachelines need to be read, thereby requiring 32K_(v) clocks, where thenumber of clocks has been doubled to account for the 50% efficiency inaccessing the SDRAM. In general, addition of J+1 virtual users to thesystem at a time, requires 32K_(v)(J+1) clocks.

[0462] In one example where there are 155 active virtual users and a newvoice user is added to the system, the time required to read in theC-matrix elements can be 32(155)(1+1) clocks/(133 clocks/μs)=74.6 μs.The present industry standard hold time t_(h) for a voice call is 140 s.The average rate λ of users added to the system can be determined fromλt_(h)=K, where K is the average number of users utilizing the system.For K=100 users, λ=100/140 s=1 user are added per 1.4 s.

[0463] In another example where there are 99 active virtual users and a384 Kbps user is added to the system, the time required to read in theC-matrix elements can be 32(99)(64+1) clocks/(133 clocks/μs)=1.55 ms.However data users presumably will be added to the system moreinfrequently than voice users.

[0464] Time to Extract Elements When τ_(xy) Changes

[0465] Now suppose, for example, that user l=x lag q=y changes. Thisnecessitates fetching the elements C[m′][x][k][y][q′] for all m′, k andq′. All the q′ values will be contained typically in 1 cache line.Hence, 2(K_(v))(1)=2 K_(v) cache lines need to be read in, therebyrequiring 16K_(v) clocks, where the number of clocks has been doubled toaccount for the 50% efficiency in accessing the SDRAM. In general, whena time lag changes, there are J+1 virtual users for which the C-matrixelements need to be updated. Such updating of the C-matrix elements canrequire 16K_(v)(J+1) clocks.

[0466] In one example in which 155 active virtual users are present anda voice user's profile (one lag) changes, the time required to read inthe C-matrix elements can be 16(155)(1+1) clocks/(133 clocks/μs)=37.3μs. As discussed above, for high mobility users, such changes shouldoccur at a rate of about 1 per 100 ms per physical user. This equates toabout once per 1.33 ms processing interval, if there are 100 physicalusers. Hence, approximately 37.3 μs will be required every 1.33 ms.

[0467] In another example where there are 99 virtual users and a 384Kbps data user's profile (one lag) changes, the time required to read inthe C-matrix elements can be 16(99)(64+1) clocks/(133 clocks/μs)=0.774ms. However data users will have lower mobility and hence such changesshould occur infrequently.

[0468] Writing C-Matrix Elements to L2 Cache

[0469] Consider again the case where user l=x is added to the system. Insuch a case, the elements C[m′][x][k][q][q′] for all m′, k, q and q′need to be written to cache. If there are K_(v) active virtual users,4K_(v)L² bytes need to be written, where the number of bytes have beendoubled because the elements are complex. In general, addition of J+1virtual users to the system at a time will require 4K_(v)L²(J+1) bytesto be written to L2 cache.

[0470] In one example, there are 155 active virtual users and a newvoice user is added to the system. In this case, the time required towrite the C-matrix elements can be 4(155)(16)(1+1) bytes/(2128bytes/μs)=9.3 μs.

[0471] In another example, there are 99 active virtual users and a 384Kbps user is added to the system. In such a case, the time required towrite the C-matrix elements can be 4(99)(16)(64+1) bytes/(2128bytes/μs)=193.5 μs. Data users are typically added to the system moreinfrequently than voice users.

[0472] Time to Extract Elements When τ_(xy) Changes

[0473] Consider a situation in which for user l=x lag q=y changes. Insuch a case, the elements C[m′][x][k][q][q′] for all m′, k and q′ needto be written. If there are K_(v) active virtual users, 4K_(v)L bytesneed to be written, where the number of the bytes has been doubled sincethe elements are complex. In general, addition of J+1 virtual users thesystem at a time will require 4K_(v)L(J+1) bytes to be written to L2cache.

[0474] In one example, there are 155 active virtual users and a voiceuser's profile (one lag) changes. In such a case, the time required towrite the C-matrix elements will be 4(155)(4)(1 +1) bytes/(2128bytes/μs)=2.33 μs.

[0475] In a second case, there are 99 active virtual users and a 384Kbps data user's profile (one lag) changes. Then, the time required towrite the C-matrix elements will be 4(99)(4)(64+1)bytes/(2128bytes/μs)=48.4 μs. However data users will have lower mobility and hencesuch changes typically occur infrequently.

[0476] Packing C-Matrix Elements in L2 Cache

[0477] In this exemplary embodiment, the C-matrix elements are packed inmemory every time a new user is added to or deleted from the system, andevery time a new user becomes active or inactive. In this embodiment,the size of the C-matrix is 2(3/2)(K_(v)L)²=3(K_(v)L)² bytes. If threeprocessors are utilized, the size per processor is (K_(v)L)² bytes.Hence, the total time required for moving the entire matrix within L2cache is 2(K_(v)L)² bytes/(2128 bytes/μs), where the factor of 2accounts for read and write. By way of example, if there are 155 activevirtual users, the time required to move the C-matrix elements is2(155*4)² bytes/(2128 bytes/μs)=0.361 ms, whereas if there are 99 activevirtual users the time required to move the C-matrix elements is2(99*4)² bytes/(2128 bytes/μs)=0.147 ms.

[0478] Hardware Calculation of Γ-Matrix Elements

[0479] As discussed above, the C-matrix elements can be represented interms of the underlying code correlations in accord with the followingrelation: $\begin{matrix}{\begin{matrix}{{C_{{lkqq}^{\prime}}\left\lbrack m^{\prime} \right\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{s_{k}\left\lbrack {{nN}_{c} + {m^{\prime}T} + {\hat{\tau}}_{lq} - {\hat{\tau}}_{{kq}^{\prime}}} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}{\sum\limits_{p}{g\left\lbrack {{\left( {n - p} \right)N_{c}} +} \right.}}}}} \\{{\left. {{m^{\prime}T} + {\hat{\tau}}_{lq} - {\hat{\tau}}_{{kq}^{\prime}}} \right\rbrack} \cdot {c_{k}\lbrack p\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}{\sum\limits_{m}{{g\left\lbrack {{mN}_{c} + \tau} \right\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack} \cdot {c_{l}^{*}\lbrack n\rbrack}}}}}} \\{= {\sum\limits_{m}{{{g\left\lbrack {{mN}_{c} + \tau} \right\rbrack} \cdot \frac{1}{2N_{l}}}{\sum\limits_{n}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}}} \\{= {\sum\limits_{m}{{g\left\lbrack {{mN}_{c} + \tau} \right\rbrack} \cdot {\Gamma_{lk}\lbrack m\rbrack}}}}\end{matrix}\begin{matrix}{{\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}} \\{\tau \equiv {{m^{\prime}T} + {\hat{\tau}}_{lq} - {\hat{\tau}}_{{kq}^{\prime}}}}\end{matrix}} & (33)\end{matrix}$

[0480] The Γ-matrix represents the correlation between the complex usercodes. The complex code for user l is assumed to be infinite in length,but with only N_(l) non-zero values. The non-zero values are constrainedto be ±1±j. The Γ-matrix can be represented in terms of the real andimaginary parts of the complex user codes as follows: $\begin{matrix}\begin{matrix}{{\Gamma_{lk}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{c_{l}^{*}\lbrack n\rbrack} \cdot {c_{k}\left\lbrack {n - m} \right\rbrack}}}}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}{\left\{ {{c_{l}^{R}\lbrack n\rbrack} - {{jc}_{l}^{I}\lbrack n\rbrack}} \right\} \cdot \left\{ {{c_{k}^{R}\left\lbrack {n - m} \right\rbrack} + {{jc}_{k}^{I}\left\lbrack {n - m} \right\rbrack}} \right\}}}}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}\left\{ {{{c_{l}^{R}\lbrack n\rbrack} \cdot {c_{k}^{R}\left\lbrack {n - m} \right\rbrack}} + {{c_{l}^{I}\lbrack n\rbrack} \cdot {c_{k}^{I}\left\lbrack {n - m} \right\rbrack}} +} \right.}}} \\{\left. {{{{jc}_{l}^{R}\lbrack n\rbrack} \cdot {c_{k}^{I}\left\lbrack {n - m} \right\rbrack}} - {{{jc}_{l}^{I}\lbrack n\rbrack} \cdot {c_{k}^{R}\left\lbrack {n - m} \right\rbrack}}} \right\}} \\{= {{\Gamma_{lk}^{RR}\lbrack m\rbrack} + {\Gamma_{lk}^{II}\lbrack m\rbrack} + {j\left\{ {{\Gamma_{lk}^{RI}\lbrack m\rbrack} - {\Gamma_{lk}^{IR}\lbrack m\rbrack}} \right\}}}}\end{matrix} & (34)\end{matrix}$

[0481] where $\begin{matrix}\begin{matrix}{{\Gamma_{lk}^{RR}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{c_{l}^{R}\lbrack n\rbrack} \cdot {c_{k}^{R}\left\lbrack {n - m} \right\rbrack}}}}} \\{{\Gamma_{lk}^{II}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{c_{l}^{I}\lbrack n\rbrack} \cdot {c_{k}^{I}\left\lbrack {n - m} \right\rbrack}}}}} \\{{\Gamma_{lk}^{RI}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{c_{l}^{R}\lbrack n\rbrack} \cdot {c_{k}^{I}\left\lbrack {n - m} \right\rbrack}}}}} \\{{\Gamma_{lk}^{IR}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{c_{l}^{I}\lbrack n\rbrack} \cdot {c_{k}^{R}\left\lbrack {n - m} \right\rbrack}}}}}\end{matrix} & (35)\end{matrix}$

[0482] Consider any one of the above real correlations, denoted$\begin{matrix}{{\Gamma_{lk}^{XY}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{{c_{l}^{X}\lbrack n\rbrack} \cdot {c_{k}^{Y}\left\lbrack {n - m} \right\rbrack}}}}} & (36)\end{matrix}$

[0483] where X and Y can be either R or I. Since the elements of thecodes are now constrained to be ±1 or 0, the following relation can bedefined:

c _(l) ^(x) [n]=(1−2γ_(l) ^(x) [n])·m _(l) ^(x) [n]  (37)

[0484] where γ_(l) ^(x)[n] and m_(l) ^(x)[n] are both either zero orone. The sequence m_(l) ^(x)[n] is a mask used to account for values ofc_(l) ^(x)[n] that are zero. With these definitions, the above Equation(4) becomes $\begin{matrix}{\begin{matrix}{{\Gamma_{lk}^{XY}\lbrack m\rbrack} \equiv {\frac{1}{2N_{l}}{\sum\limits_{n}{\left( {1 - {2{\gamma_{l}^{X}\lbrack n\rbrack}}} \right) \cdot {m_{l}^{X}\lbrack n\rbrack} \cdot \left( {1 - {2{\gamma_{k}^{Y}\left\lbrack {n - m} \right\rbrack}}} \right) \cdot}}}} \\{{m_{k}^{Y}\left\lbrack {n - m} \right\rbrack}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}{\left( {1 - {2{\gamma_{l}^{X}\lbrack n\rbrack}}} \right) \cdot \left( {1 - {2{\gamma_{k}^{Y}\left\lbrack {n - m} \right\rbrack}}} \right) \cdot {m_{l}^{X}\lbrack n\rbrack} \cdot}}}} \\{{m_{k}^{Y}\left\lbrack {n - m} \right\rbrack}} \\{= {\frac{1}{2N_{l}}{\sum\limits_{n}{\left\lbrack {1 - {2\left( {{\gamma_{l}^{X}\lbrack n\rbrack} \oplus {\gamma_{k}^{Y}\left\lbrack {n - m} \right\rbrack}} \right)}} \right\rbrack \cdot {m_{l}^{X}\lbrack n\rbrack} \cdot}}}} \\{{m_{k}^{Y}\left\lbrack {n - m} \right\rbrack}} \\{= {\frac{1}{2N_{l}}\left\{ {{\sum\limits_{n}{{\cdot {m_{l}^{X}\lbrack n\rbrack}} \cdot {m_{k}^{Y}\left\lbrack {n - m} \right\rbrack}}} -} \right.}} \\{\left. {2{\sum\limits_{n}{\left( {{\gamma_{l}^{X}\lbrack n\rbrack} \oplus {\gamma_{k}^{Y}\left\lbrack {n - m} \right\rbrack}} \right) \cdot {m_{l}^{X}\lbrack n\rbrack} \cdot {m_{k}^{Y}\left\lbrack {n - m} \right\rbrack}}}} \right\}} \\{= {\frac{1}{2N_{l}}\left\{ {{M_{lk}^{XY}\lbrack m\rbrack} - {2{N_{lk}^{XY}\lbrack m\rbrack}}} \right\}}}\end{matrix}{{M_{lk}^{XY}\lbrack m\rbrack} \equiv {\sum\limits_{n}{{\cdot {m_{l}^{X}\lbrack n\rbrack}} \cdot {m_{k}^{Y}\left\lbrack {n - m} \right\rbrack}}}}{{N_{lk}^{XY}\lbrack m\rbrack} \equiv {\sum\limits_{n}{\left( {{\gamma_{l}^{X}\lbrack n\rbrack} \oplus {\gamma_{k}^{Y}\left\lbrack {n - m} \right\rbrack}} \right) \cdot {m_{l}^{X}\lbrack n\rbrack} \cdot {m_{k}^{Y}\left\lbrack {n - m} \right\rbrack}}}}} & (38)\end{matrix}$

[0485] where ⊕ indicates modulo-2 addition (or logical XOR).

[0486] In addition to configurations discussed elsewhere herein, FIGS.17, 18 and 19 illustrate exemplary hardware configurations for computingthe functions M_(lk) ^(XY)[m] and N_(lk) ^(XY)[m] for calculating theΓ-matrix elements. Once the functions M_(lk) ^(XY)[m] and N_(lk)^(XY)[m] are obtained, the remaining calculations for obtaining theΓ-matrix elements can be performed in software, or hardware. In thisexemplary embodiment, these remaining calculations are performed insoftware. More particularly, FIG. 17 shows a register having an initialconfiguration subsequent to loading a code and a mask sequences.Further, FIG. 18 depicts a logic circuit for performing the requisiteboolean functions. FIG. 19 depicts the configuration of the registerafter implementing a number of shifts.

[0487] The four functions Γ_(lk) ^(XY)[m] corresponding to X, Y=R, Iwhich are components of Γ_(lk)[m] can be calculated in parallel. ForK_(v)=200 virtual users, and assuming that 10% of all (l, k) pairs needto be calculated in 2 ms, then for real-time operation, 0.10(200)²=4000Γ_(lk)[m] elements (all shifts) need to be computed in 2 ms, or about 2Melements (all shifts) per second. For K_(v)=128 virtual users, therequirement drops to 0.8192M elements (all shifts) per second.

[0488] In this embodiment, the Γ_(lk)[m] elements are calculated for all512 shifts. However, not all of these shifts are needed. Thus, it ispossible to reduce the number of calculations per Γ_(lk)[m] elements bycalculating only those elements that are needed.

[0489] As described in more detail elsewhere herein, in one hardwareimplementation of the invention, a single processor is utilized forperforming the C-matrix calculations whereas a plurality of processors,for example, three processors, are employed for the R-matrixcalculations, which are considerably more complex. In what follows, aload balancing method is described that calculates optimum R-matrixpartitioning points in normalized virtual user space to provide anequal, and hence balanced, computational load per processor. Moreparticularly, it is shown that a closed form recursive solution existsthat can be solved for an arbitrary number of processors.

[0490] Balancing Computational Load Among Processors for ParallelCalculation of R-Matrix

[0491] As a result of the following symmetry condition, only half of theR-matrix elements need to be explicitly calculated:

R _(lk)(m)=ξR _(k,l)(−m).  (39)

[0492] In essence, only two matrices need to be calculated. One of thesematrices is combination of R(1) and R(−1), and the other is the R(0)matrix. In this case, the essential R(0) matrix elements have atriangular structure. The number of computations performed to generatethe raw data for the R(1)/R(−1) and R(0) matrices are combined andoptimized as a single number. This approach is adopted due to the reuseof the X matrix outer product values (see the above Equation (8)) acrossthe two R-matrices. Combining the X matrix and correlation valuesdominate the processor utilization since they represent the bulk of thecomputations. In this embodiment, these computations are employed as acost metric for determining the optimum loading of each processor.

[0493] The optimization problem can be formulated as an equal areaproblem, where the solution results in equal partition areas. Since themajor dimensions of the R-matrices are given in terms of the number ofactive virtual users, the solution space for the optimization problemscan be defined in terms of the number of virtual users per processor. Itis clear to those skilled in the art that the solution can be applicableto an arbitrary number of virtual users by normalizing the solutionspace by the number of virtual users.

[0494] With reference back to FIG. 10, the computations of theR(1)/R(−1) matrix can be represented by a square HJKM while thecomputations of the R(0) matrix can be represented by a triangle ABC.From elementary geometry, the area of a rectangle of length b and heighth is given by:

A_(r)=bh.  (40)

[0495] and the area of a triangle with a base width b and a height h isgiven by $\begin{matrix}{A_{t} = {\frac{1}{2}{{bh}.}}} & (41)\end{matrix}$

[0496] Accordingly, a combined area of a rectangle A_(ri) and a triangleA_(ti) having a common height a_(i) is given by the following relation:$\begin{matrix}{\begin{matrix}{A_{t} = {A_{ti} + A_{ti}}} \\{= {{a_{i}a_{3}} + {\frac{1}{2}a_{i}^{2}}}} \\{= {a_{i} + {\frac{1}{2}a_{i}^{2}}}}\end{matrix}.} & (42)\end{matrix}$

[0497] wherein A_(i) provides the area of a region below a givenpartition line. For example, A₂ provides the area within the rectangleHQRM plus the region within triangle AFG. The difference in the area ofsuccessive partition regions is employed to form a cost function. Moreparticularly, $\begin{matrix}\begin{matrix}{B_{i} = {A_{i} - A_{i - 1}}} \\{= {{\frac{1}{2}a_{i}^{2}} + a_{i} - {\frac{1}{2}a_{i - 1}^{2}} - a_{i - 1}}}\end{matrix} & (43)\end{matrix}$

[0498] For an optimum solution, B_(i)'s corresponding to i=1, 2, . . . ,N, where N is the number of processors performing the calculations, areequal. Because the total normalized load is equal to A_(N), the load perprocessor is equal to A_(N)/N. That is $\begin{matrix}{{B_{i} = {\frac{A_{N}}{N} = {\frac{A_{3}}{3} = \frac{3}{2N}}}},} & (44)\end{matrix}$

[0499] for i=1, 2, . . . , N.

[0500] By combining the above equations for B_(i), the solution fora_(i) can be found by finding the roots of the following equation:$\begin{matrix}{{{\frac{1}{2}a_{i}^{2}} + a_{i} - {\frac{1}{2}a_{i - 1}^{2}} - a_{i - 1} - \frac{3}{2N}} = 0.} & (45)\end{matrix}$

[0501] Hence, the solution of a_(i) is given as follows: $\begin{matrix}{{a_{i} = {{- 1} \pm \sqrt{1 + a_{i - 1}^{2} + {2a_{i - 1}} + \frac{3}{N}}}},} & (46)\end{matrix}$

[0502] The negative roots of the above solution for a_(i) are discardedbecause the solution space falls in a range [0,1]. Although it appearsthat a solution of a_(i) requires first obtaining values of a_(i)−1,expanding the recursion relations of the a_(i) and utilizing the factthat a₀ equals 0 results in obtaining the following solution for a_(i)that does not require obtaining a_(i)−1: $\begin{matrix}{a_{i} = {{- 1} + \sqrt{1 + \frac{3i}{N}}}} & (47)\end{matrix}$

[0503] The table below illustrates the normalized partition values oftwo, three, and four processors. To calculate the actual partitionvalues, the number of active virtual users is multiplied by thecorresponding table entries. Since a fraction of a user can not beallocated, a ceiling operation can be performed that biases the numberof virtual users per processor towards the processors whose loadingfunction is less sensitive to perturbations in the number of usersLocation Two processors Three processors Four processors a₁${- 1} = {\sqrt{\frac{5}{2}}(0.5811)}$

${- 1} + {\sqrt{2}(0.4142)}$

${- 1} + {\sqrt{\frac{7}{4}}(0.3229)}$

a₂ — ${- 1} + {\sqrt{3}(0.7321)}$

${- 1} + {\sqrt{\frac{5}{2}}(0.5811)}$

a₃ — — ${- 1} + {\sqrt{\frac{13}{4}}(0.8028)}$

[0504] The above methods for calculating the R-matrix elements can beimplemented in hardware and/or software as illustrated elsewhere herein.With reference to FIG. 20, in one embodiment, the above calculations areperformed by utilizing a single card that is populated with four PowerPC 7410 processors. These processors employ the AltiVec SIMD vectorarithmetic logic unit which includes 32 128-bit vector registers. Theseregisters can hold either four 32-bit float, or four 32-bit integers, oreight 16-bit shorts, or sixteen 8-bit characters. Two vector SIMDoperations can be performed by clock. The clock rate utilized in thisembodiment is 400 Mz, although other clock rates can also employed. Eachprocessor has 32 KB of L1 cache and 2 MB of 266 MHz L2 cache. Hence, themaximum theoretical performance level of these processors is 3.2 GFLOPS,6.4 GOPS (16-bit), or 12.8 GOPS (8-bit). In this exemplary embodiment, acombination of floating-point, 16-bit fixed-point and 8-bit fixed-pointcalculations are utilized.

[0505] With continued reference to FIG. 20, the calculation of theC-matrix elements are performed by a single processor 220. In contrast,the calculation of the R-matrix elements are divided among threeprocessors 222, 224, and 226. Further, a RACE++ 266 MB/sec 8-portswitched fabric 228 interconnects the processors. The high bandwidth ofthe fabric allows transfer of large amounts of data with minimal latencyso as to provide efficient parallelism of the four processors.

[0506] Vector Processor-Based R-Matrix Generation

[0507] Vector processing is beneficially employed, in one embodiment ofthe invention, to speed calculations performed by the processor card ofFIGS. 2 and 3. Specifically, the AltiVec™ vector processing resources(and, more particularly, instruction set) of the Motorola PowerPC 7400processor used in node processors 228 are employed to speed calculationof the R-matrix. These processors include a single-instructionmultiple-data (SIMD) vector arithmetic logic unit which includes 32128-bit input vector units. These units can hold either four 32-bitintegers, or eight 16-bit integers, or even sixteen 8-bit integers. Theclock rate utilized in this embodiment is 400 Mz, although other clockrates can be also employed.

[0508] Of course, those skilled in the art will appreciate that othervector processing resources can be used in addition or instead. Thesecan include SIMD coprocessors or node processors based on other chipsets, to name a few. Moreover, those skilled in the art will appreciatethat, while the discussion below focuses on use of vector processing tospeed calculation of the R-matrix, the techniques described below can beapplied to calculating other matrices of the type described previouslyas well, more generally, to other calculations used for purposes of CDMAand other communications signal processing.

[0509] In the illustrated embodiment, a mapping vector is utilized tocreate a mapping between each physical user and its associated (or“decomposed”) virtual users. This vector is populated during thedecomposition process which, itself, can be accomplished in aconventional manner known in the art. The vector is used, for example,during generation of the R-matrix as described below.

[0510] As further evident in the discussion below, the X-matrix (seeEquation (8)), is arranged such that a “strip-mining” method of theboundary elements can be performed to further increase speed andthroughput. The elements of that matrix are arranged such thatsuccessive ones of them can be stripped to generate successive elementsin the R-matrix. This permits indices to be incremented rather thancalculated. The elements are, moreover, arranged in a buffer such thatadjacent elements can be multiplied with adjacent element of theC-matrix, thereby, limiting the number of required indices to two withinthe iterative summation loops.

[0511] In the discussion that follows, a node processor 228 operating asa vector processor is referred to as vector processor 410. FIG. 21 is ablock diagram depicting the architecture and operation of one such nodeprocessor 228, and its corresponding vector processor 410, used in anembodiment of the invention to calculate the R-matrix 428 using integerrepresentations of the C-matrix 424 and waveform amplitudes 426. Tofacilitate a complete understanding of the illustrated embodiments, onlya sampling of operands are illustrated, e.g., a few elements each of theC-matrix 424, complex amplitudes 426 and R-matrix 428. In actualoperation of a system according to the invention, the vector processor410 can used to process matrices containing hundreds or thousands ofelements.

[0512] As shown in the drawing, the illustrated node processor 228 isconfigured via software instructions to execute a floating point tointeger transformation process 406 and an integer to floating pointtransformation process 412, well as to serve as a vector processor 410.The relationship and signalling between these modes is depicted in thedrawing.

[0513] By way of overview, and as discussed above, one or morecode-division multiple access (CDMA) waveforms or signals transmitted,e.g., from a user cellular phone, modem or other CDMA signal source aredecomposed into one or more virtual user waveforms. The virtual user isdeemed to “transmit” a single bit per symbol period of that receivedCDMA waveform. In turn, each of the virtual user waveforms is processedaccording to the methods and systems described above.

[0514] In some embodiments, waveform processing is performed usingfloating-point math, e.g., for generating the gamma-matrix, C-matrix,R-matrix, and so on, all in the manner described above. However, in anembodiment of the invention, e.g., reflected in FIG. 21, integer math isperformed on the vector processor 410, taking advantage ofblock-floating point representation of the operands. This speedswaveform processing, albeit at the cost of accuracy. However, in theillustrated embodiment, a balance is achieved by through use of 16-bitblock-floating point representation, e.g., in lieu of conventional32-bit floating-point representations. Those skilled in the art willappreciate that block-floating representations of other bit widths couldbe used instead, depending on implementation requirements.

[0515] Referring to FIG. 21, the C-matrix 424 is generated by the nodeprocessor 228 as described above, and is stored in memory accordingly ina floating-point representation, e.g., C₀ 401, C₁ 402, and so on.Further, the amplitudes 426 are stored in memory as floating-pointrepresentations. Both sets of representations are transformed intofloating-block format via a transformation process 406 which generates acommon exponent 414 and a 16-bit integer for each operand. Thetransformation process 416 stores two integers in each word, e.g., C₀408 a, C₁ 408 b, and a₀ 409 a, a₁ 409 b, and the corresponding blockexponent 414. The transformation process 414 can be performed viaspecial purpose function or through use of extensions to the Cprogramming language, as can be seen in a programming listing that isfurther described. The integers stored in memory, e.g., 408, 409, aremoved by the transformation process 406 to the vector processor 410 forprocessing.

[0516] The vector processor 410 includes two input vector units 416,418, an output vector unit 420, and an arithmetic processor 422. Eachvector unit is 128-bits in length, hence, each can store eight of the16-bit integer operands. The arithmetic processor 422 has a plurality ofoperating elements, 422 a through 422 c. Each of the operating element422 a through 422 c applies functionality to a set of operands stored inthe input vector units 416, 418, and stores that processed data in theoutput vector 420. For example, the operating element 422 a performsfunctionality on operands C₀ 416 a and a₀ 418 a and generates R₀ 420 a.The arithmetic processor 422 can be programed via C programminginstructions, or by a field programmable gate array or other logic.

[0517] Although vector processor 410 includes two input vector units416, 418, in other embodiments it can have numerous vector units, thatcan be loaded with additional C-matrix and complex amplituderepresentations at the same time. Further, the operands can be stored ina non-sequential order to accommodate increased throughput via storingoperands according to a first-used order.

[0518] As noted above, one way to program the arithmetic processor 422is through extensions to a high level programming language. One suchprogram, written in C, suitable for instruction the vector processor 422to generate the R-matrix is as follows: #include “mudlib.h” #defineDO_CALC STATS 0 #define DO_TRUNCATE 1 #define DO_SATURATE 1 #defineDO_SQUELCH 0 #define SQUELCH_THRESH 1.0 #define TRUNCATE_BIAS 0.0 #ifDO_TRUNCATE #define SATURATE_THRESH (128.0 + TRUNCATE_BIAS) #else#define SATURATE_THRESH 127.5 #endif #define SATURATE( f ) \ { \ if ((f) >= SATURATE_THRESH ) f = (SATURATE_THRESH − 1.0); \ else if ( (f) <−SATURATE_THRESH ) f = −SATURATE_THRESH; \ } #if DO_TRUNCATE #if 0#define BF8_FIX ( f ) ((BF8) (FABS(f) <= TRUNCATE_BIAS) ? 0 : \ (((f) >0.0) ? ((f) − TRUNCATE_BIAS) : \ ; ((f) + TRUNCATE BIAS))) #defineBF8_FIX ( f ) ((BF8)(f)) #else #define BF8_FIX ( f ) ((BF8) (((((f) <0.0)) && ((f) == (float) ((int) (f)))) ?\ ((f) + 1.0) : (f))) #endif#else #define BF8_FIX ( f ) ((BF8)(((f) >= 0.0) ? ((f)+0.5) :((f)−0.5))) #endif #define UPDATE_MAX ( f, max ) \ if ( FABS( f ) > max) max = FABS ( f. ); #define uchar unsigned char #define ushort unsignedshort #define ulong unsigned long #if DO_CALC_STATS static floatmax_R_value; #endif void gen_X_row ( COMPLEX_BF16 *mpath1_bf,COMPLEX_BF16 *mpath2_bf, COMPLEX_BF16 *X_bf, int phys_index, inttot_phys_users ); void gen_R_sums ( COMPLEX_BF16 *X_bf, COMPLEX_BF8*corr_bf, uchar *ptov_map, BF32 *R_sums, int num_phys_users ); voidgen_R_sums2 ( COMPLEX_BF16 *X_bf, COMPLEX_BF8 *corra_bf, COMPLEX_BF8*corrb_bf, uchar *ptov_map, BF32 *R_sumsa, BF32 *R_sumsb, intnum_phys_users ); void gen_R_matrices ( BF32 *R_sums, float *bf_scalep,float *inv_scalep, float *scalep, BF8 *no_scale_row_bf, BF8*scale_row_bf, int num_virt_users ); void mudlib_gen_R ( COMPLEX_BF16*mpath1_bf, /* ANTENNA DATA 1: TWO AMPLITUDE  DATA VALUES a hat FOR EACHUSER  */ BCOMPLEX_BF16 *mpath2_bf, /* ANTENNA DATA 2 */ COMPLEX_BF8*corr_0_bf, /* adjusted for starting physical  user */ /* C MATRIX,I.E., C(0), SYMBOL YOU  ARE ON VERSUS OTHER SYMBOLS */ COMPLEX_BF8*corr_1_bf, /* adjusted for starting physical  user */ /* C MATRIX. THISIS A VIRTUAL  USER BY VIRTUAL USER_MATRIX.  EACH USER HAS 16 VALUES THAT CORRELATE THAT USER TO OTHER  USERS */ uchar *ptov_map, /* no more than256 virts. per phys  */ /* MAPPING OF PHYSICAL TO  VIRTUAL USERS MAP. INFURTHER  EMBODIMENTS, THIS COULD  DYNAMICALLY CHANGE AS USERS  ENTERINTO AND LEAVE SYSTEM */ float *bf_scalep, /* scalar: always a power of2 */ /* VECTOR WITH SCALAR FOR EACH  VIRTUAL USER -- NOTWITHSTANDING  */float *inv_scalep, /* start at O'th physical user */ float *scalep, /*start at O'th physical user */ char *L1 cachep, /* temp: 32K bytes,32-byte aligned  */ /* OUTPUTS (BEGINNING AT NEXT LINE)  */ BF8*R0_upper_bf, /* UPPER PART OF R(1) MATRIX -- A  TRIANGULAR PACKEDMATRIX */ BF8 *R0_lower_bf, /* LOWER PART OF R(0) MATRIX */ BF8*R1_trans_bf, /* TRANSPOSED FORM OF R(0) */ BF8 *R1m_bf, /* R(−1) -->“m” STANDS FOR −1 */ int tot_phys_users, /* TOTAL PHYSICAL USERS */ inttot_virt_users, /* SUM OF VIRTUAL USERS */ int start_phys_user, /*zero-based starting row  (inclusive) */ /* STARTING PHYSICAL USER TOWHICH  THIS PR0CESSOR IS ASSIGNED */ int start_virt_user, /* relative tostart_phys_user */ /* STARTING VIRTUAL USER TO WHICH  THIS PR0CESSOR ISASSIGNED */ /* NOTE: THIS IS AN ADVANTAGE  IN ALLOWING US TO PARTITION A GIVEN PHYSICAL USER TO MULTIPLE  PROCESSORS */ int end_phys_user, /*zero-based ending row inclusive)  */ /* SAME AS ABOVE, BUT END VALUES */int end_virt_user /* relative to end_phys_user */ ) { COMPLEX_BF16*X_bf; BF32 *R_sums0, *R_sums1; /* BEGINNING OF PARTITIONING AND PARAMETER SET-UP LOGIC */ uchar *R0_ptov_map; int bump, byte_offset, i,iv, last_virt_user, int R0_align, R0_skipped_virt_users, R0_tcols,R0_virt_users, R1_tcols; #if DO_CALC_STATS max_R_value = 0.0; #endifX_bf = (COMPLEX_BF16 *) L1_cachep; byte offset = tot_phys_users *NUM_FINGERS_SQUARED * sizeof (COMPLEX BF1F); R_sums0 = (BF32 *)(((ulong)X_bf + byte_offset + R_MATRIX_ALIGN_MASK) &˜R_MATRIX_ALIGN_MASK); byte_offset = tot_virt_users * sizeof (BF32);R_sums1 = (BF32 *) (((ulong) R_sums0 + byte_offset +R_MATRIX_ALIGN_MASK) & ˜R_MATRIX_ALIGN_MASK); R0 ptov_map = (uchar *)(((ulong) R_sums1 + byte_offset + R_MATRIX_ALIGN_(—) MASK) &˜R_MATRIX_ALIGN_MASK); R1_tcols = (tot_virt_users + R_MATRIX_ALIGN_MASK)& ˜R_MATRIX_ALIGN_MASK; R0_virt_users = 0; for ( i = start_phys_user; i< tot_phys_users; i++ ) { R0_virt_users += (int)ptov map[I];R0_ptov_map[I] = ptov_map[I]; } R0_ptov_map [start_phys_user] −= startvirt user; R0_skipped_virt_users = tot_virt_users − RU_virt_users +start_virt_user; R0_virt_users −= (start_virt_user + 1); --inv_scalep;/* predecrement to allow for common  indexing */ for ( i =start_phys_user; i <= end_phys_user; i++ ) { /* LOOP OVER ALL PHYSICALUSERS (ASSIGNED TO THIS PR0CESSOR) */ gen_X_row ( /* FIND C CODE THATPERTAINS TO THIS */ mpath1_bf, mpath2_bf, X_bf, i, tot_phys users );--R0_ptov_map[i]; /* excludes R0 diagonal */ last_virt_user = (i <end_phys_user) ? ((int)ptov map[I] − 1) : end_virt_user; for ( iv =start_virt_user; (iv + 1) <= last virt user; iv += 2 ) { gen_R_sums2 (X_bf + (i * NUM_FINGERS_SQUARED), corr_0_bf, corr_0_bf + ((R0_virt_users − 1) * NUM_FINGERS_SQUARED), R0_ptov map + i, R_sums0 +(R0_skipped_virt_users + 1), R_sums1 + (R0_skipped_virt_users + 1),tot_phys_users − i ); R0_tcols = R1_tcols − (R0_skipped_virt_users &˜R_MATRIX_ALIGN_MASK); R0_align = (R0_skipped_virt_users &R_MATRIX_ALIGN_MASK) + 1; gen R_matrices ( R_sums0 +(R0_skipped_virt_users + 1), bf scalep, inv scalep + (R0 skippedvirt_users + 1), scalep + (R0_skipped_virt_users + 1), R0 lower bf + R0align, R0 upper bf + R0 align, R0 virt_users ); R0_upper_bf [ R0_align −1 ] = 0; /* zero diagonal element */ R0_lower_bf += R0_tcols;R0_upper_bf += R0_tcols; R0_tcols = R1_tcols − ( (R0skipped_virt_users + 1) & ˜R_MATRIX_ALIGN_MASK); R0_align = ((R0_skipped_virt_users + 1) & R_MATRIX_ALIGN_MASK) + 1; gen_R_matrices (R_sums1 + (R0_skipped_virt_users + 2), bf_scalep, inv_scalep +(R0_skipped_virt_users + 2), scalep + (R0 skipped virt_users + 2),R0_lower_bf + R0_align, R0_upper_bf + R0_align, R0_virt_users − 1 );R0_upper_bf [ R0_align − 1 ] = 0; /* zero diagonal element */R0_lower_bf += R0_tcols; R0_upper_bf += R0_tcols; /* * create ptovmap[i] number of 32-element dot products involving * X_bf [i] andcorr_l_bf [i] [j] where 0 < j < ptov_map[i] */ gen_R_sums2 ( X_bf,corr_1_bf, corr_1_bf + (tot_virt_users * NUM_FINGERS_SQUARED), ptov_map,R sums0, R sums1, tot phys users ); /* * scale the results and createtwo output rows (1 per matrix) */ gen_R_matrices ( R_sums0, bf_scalep,inv_scalep + (R0_skipped_virt_users + 1), scalep, R1_trans_bf, R1m_bf,tot_virt_users ); R1_trans_bf += R1_tcols; R1m_bf += R1_tcols;gen_R_matrices ( R_sums1, bf_scalep, inv_scalep +(R0_skipped_virt_users + 2), scalep, R1_trans_bf, R1m_bf, tot_virt_users); R1_trans_bf += R1_tcols; R1m_bf += R1_tcols; corr_0_bf += (((2 *R0_virt_users) − 1) * NUM FINGERS SQUARED); corr_1_bf += ((2 *tot_virt_users) * NUM_FINGERS_SQUARED); R0_ptov_map[i] −= 2;R0_virt_users −= 2; R0_skipped_virt_users += 2; } if ( iv <= last virtuser ) { bump = R0_ptov_map [ i ] ? 0 : 1; gen_R_sums ( X_bf + ((i +bump) * NUM_FINGERS_SQUARED), corr_0_bf, R0_ptov_map + i + bump,R_sums0 + (R0_skipped_virt_users + 1), tot_phys_users − i − bump );R0_tcols = R1_tcols − (R0_skipped_virt_users & ˜R_MATRIX_ALIGN_MASK);R0_align = (R0_skipped_virt_users & R_MATRIX_ALIGN_MASK) + 1;gen_R_matrices ( R_sums0 + (R0_skipped_virt_users + 1), bf_scalep,inv_scalep + (R0_skipped_virt_users + 1), scalep +(R0_skipped_virt_users + 1), R0_lower_bf + R0_align, R0_upper_bf +R0_align, R0_virt_users ); R0_upper_bf [ R0_align − 1 ] = 0; /* zerodiagonal element */ R0_lower_bf += R0_tcols; R0_upper_bf += R0_tcols;/* * create ptov map[i] number of 32-element dot products involving *X_bf [i] and corr_1_bf [i] [j] where 0 < j < ptov_map[i] */ gen_R_sums (X_bf, corr_1_bf, Ptov_map, R_sums0, tot_phys_users ); /* * scale theresults and create two output rows (1 per matrix) */ gen_R_matrices (R_sums0, Bf_scalep, inv_scalep + (R0_skipped_virt_users + 1), scalep,R1_trans_bf, R1m_bf, Tot_virt_users ); R1_trans_bf + = R1_tcols; R1m_bf+= R1_tcols; Corr_0_bf += (R0_virt_users * NUM_FINGERS_SQUARED);corr_l_bf += (tot_virt_users * NUM_FINGERS_SQUARED); R0_ptov_map[i] −=1; R0_virt_users −= 1; R0_skipped_virt_users += 1; } Start_virt_user =0;/* for all subsequent passes */ } #if DO_CALC_STATS printf (“max_R_value = % f\n”, max_R_value ); if ( max_R_value > 127.0 ) printf( “***** OVERFLOW *****\n” ); #endif } #if COMPILE_C /* OUTPUT PRODUCTOF TWO  ANTENNAS */ void gen_X_row ( /* EACH ANTENNA HAS TWO  VALUES PERPHYSICAL USER  */ COMPLEX_BF16 *mpath1_bf, /* 2ND ANTENNA IS DIVERSITYANTENNA */ COMPLEX_BF16 *mpath2_bf, /* RESULTING OUTPUT PR0DUCT IS REP'DBY  X sub l,k */ COMPLEX_BF16 *X_bf, int_phys_index, int_tot_phys users) { COMPLEX_BF16 *in_mpathlp, *in_mpath2p; COMPLEX_BF16 *out_mpathlp,*out_mpath2p; int i, j, q, q1; BF32 s1r, s1i, s2r, s2i; BF32 a1r, a1i,a2r, a2i; BF32 cr, ci; out_mpathlp = mpath1_bf + (phys_index *NUM_FINGERS); out_mpath2p = mpath2_bf + (phys_index * NUM_FINGERS); for( i = 0; i < tot_phys_users; i++ ) { in_mpath1p = mpath1_bf + (i *NUM_FINGERS); /* 4 complex values */ in_mpath2p = mpath2_bf + (i *NUM_FINGERS); /* 4 complex values */ j = 0; for ( q1 = 0; q1 <NUM_FINGERS; q1++ ) { s1r = (BF32) out_mpathlp [q1] .real; s1i = (BF32)out_mpathlp [q1] .imag; s2r = (BF32) out_mpath2p [q1] .real; s2i =(BF32) out_mpath2p [q1] .imag; for ( q = 0; q < NUM FINGERS; q++ ) { a1r= (BF32)in_mpathlp [q] . real; a1i = (BF32)in_mpathlp [q] . imag; a2r =(BF32) in_mpath2p [q] .real; a2i = (BF32) in_mpath2p [q] . imag; cr =(a1r * s1r) + (a1i * s1i); /* COMBO OF TWO ANTENNAS --  COULD BE MORE,OF COURSE  */ ci = (a1r * s1i) − (a1i * s1r); /* cr IS REAL PART OF ELEMENT OF X-MATRIX */ cr += (a2r * s2r) + (a2i * s2i); ci += (a2r *s2i) − (a2i * s2r); X_bf [i * NUM_FINGERS_SQUARED + j] .real = (BF16)(cr >> 16); /* BLOCK X_bf [i * NUM_FINGERS_SQUARED + j] .imag = (BF16)(ci >> 16); ++j; } } } } void gen_R_sums ( COMPLEX_BF16 *X_bf,COMPLEX_BF8 *corr_bf, uchar *ptov_map, BF32 *R_sums, int num_phys_users) { int i, j, k; BF32 sum; for ( i = 0; i < num_phys_users; i++ ) { for( j = 0; j < (int)ptov_map [i]; j++ ) { sum = 0; for ( k = 0; k < 16;k++ ) { sum += (BF32) X_bf [k] .real * (BF32) corr_bf->real; sum +=(BF32) X_bf [k] .imag * (BF32) corr_bf->imag; ++corr_bf; } *R sums++ =sum; } X_bf + = NUM_FINGERS_SQUARED; } } void gen_R_sums2 ( COMPLEX BF16+X_bf, COMPLEX BF8 *corra_bf, COMPLEX_BF8 *corrb_bf, uchar *ptov_map,BF32 *R_sumsa, BF32 *R_sumsb, int num_phys_users ) { int i, j, k; BF32suma, sumb; for ( i = 0; i < num_phys_users; i++ ) { for ( j = 0; j <(int)ptov_map[i]; j++ ) { suma = 0; sumb = 0; for ( k = 0; k < 16; k++ ){ suma += (BF32) X_bf [k] .real * (BF32) corra_bf ->real; suma += (BF32)X_bf [k] .imag * (BF32) corra_bf ->imag; sumb += (BF32) X_bf [k] .real *(BF32) corrb_bf ->real; sumb += (BF32) X_bf [k] .imag * (BF32) corrb_bf->imag; ++corra_bf; ++corrb_bf; } *R sumsa++ = suma; *R sumsb++ = sumb;} X_bf += NUM_FINGERS_SQUARED; } } void gen_R_matrices ( BF32 *R_sums,float *bf_scalep, float *inv_scalep, float *scalep, BF8*no_scale_row_bf, BF8 *scale_row_bf, int num_virt_users ) { int i; floatbf_scale, fsum, fsum_scale, inv_scale, scale; bf_scale = *bf_scalep;inv_scale = *inv_scalep; for ( i = 0; i < num_virt_users; i++ ) { scale= scalep[i]; fsum = (float) (R_sums[i]); fsum *= bf_scale; fsum_scale =fsum * inv_scale; fsum_scale *= scale; #if DO_CALC_STATS UPDATE_MAX(fsum_scale, max_R_value ) UPDATE_MAX ( fsum, max_R_value ) #endif #ifDO_SQUELCH if ( FABS ( fsum_scale ) <= SQUELCH_THRESH ) fsum_scale =0.0; if ( FABS ( fsum ) <= SQUELCH_THRESH ) fsum = 0.0; #endif #if DOSATURATE SATURATE( fsum_scale ) SATURATE( fsum ) #endifno_scale_row_bf[i] = BF8_FIX ( fsum ); scale row bf [i] = BF8_FIX(fsum_scale );\ } } #endif /* COMPILE_C */

[0519] A transformation process 412 transforms the block-floatingrepresentations stored in the output vector unit 420 into floating pointrepresentations and stores those to a memory 428. Here, the R-matrixelements stored in the output vector unit 420 are transformed intofloating-point representations, which can then be used in the mannerdescribed above for estimating symbols in the physical user waveforms.

[0520] In summary, sufficient throughput can be achieved with necessaryaccuracy using a vector processor 410 applying integer math on 16-bitblock-floating integers. Of course, in other embodiments, differentblock-floating sizes can be used depending on such criteria as thenumber of users, speed of the processors, and necessary accuracy of thesymbol estimates, to name a few. Further, like methods and logicdescribed can be used to generate other matrices (e.g., the gamma-matrixand the C-matrix) and to perform other calculations within theillustrated embodiment.

[0521] A further understanding of the operation of the illustrated andother embodiments of the invention may be attained by reference to (i)U.S. Provisional Application Serial No. 60/275,846 filed Mar. 14, 2001,entitled “Improved Wireless Communications Systems and Methods”; (ii)U.S. Provisional Application Serial No. 60/289,600 filed May 7, 2001,entitled “Improved Wireless Communications Systems and Methods UsingLong-Code Multi-User Detection'” and (iii) U.S. Provisional ApplicationSerial No. 60/295,060 filed Jun. 1, 2001 entitled “Improved WirelessCommunications Systems and Methods for a Communications Computer,” theteachings all of which are incorporated herein by reference, and a copyof the latter of which may be filed herewith.

[0522] The above embodiments are presented for illustrative purposesonly. Those skilled in the art will appreciate that variousmodifications can be made to these embodiments without departing fromthe scope of the present invention. For example, the processors could beof makes and manufactures and/or the boards can be of other physicaldesigns, layouts or architectures. Moreover, the FPGAs and other logicdevices can be software or vice versa. Moreover, it will be appreciatedthat while the illustrated embodiments decomposes physical userwaveforms to virtual user waveforms, the mechanisms described herein canbe applied, as well, without such decomposition, and that, accordingly,the terms “waveform” or “user waveform” should be treated as referringto either physical or virtual waveforms unless otherwise evident fromcontext.

Therefore, in view of the foregoing, what we claim is: WirelessCommunications Systems and Methods for Multiple Operating SystemMultiple User Detection
 1. A communications device for detecting usertransmitted symbols encoded in spread spectrum waveforms (hereinafter“user waveforms”) comprising a first process operating under a firstoperating system and executing a first set of communication tasks fordetecting user transmitted symbols encoded in the user waveforms, asecond process operating under a second operating system, and executinga second set of communication tasks for detecting user transmittedsymbols encoded in the user waveforms, where the first and secondoperation systems differ, a protocol translator coupled to the first andsecond processes and translating communications in between, the firstprocess sending to the second process via the protocol translator a setof executable instructions for performing at least a portion of saidsecond set of communication tasks.
 2. The device of claim 1, wherein thesecond process generates a matrix as a result of executing the set ofinstructions.
 3. The device of claim 2, wherein the matrix representsany of a correlation of code sequences for the user waveforms, across-correlation of the user waveforms based on time-lags and complexamplitudes, and estimates of user transmitted symbols embedded in theuser waveforms.
 4. The device of claim 3, wherein the second processroutes said matrix to one or more memories and devices based on aconfiguration specified by the first process.
 5. The device of claim 1,wherein the first process sends via the protocol translator informationto the second processor for configuration thereof.
 6. The device ofclaim 5, wherein the information comprises a routing map.
 7. The deviceof claim 6, wherein the second process routes a result of executing theset of instructions based on the routing map.
 8. The device of claim 7,wherein the second process generates a matrix as the result of executingthe set of instructions.
 9. The device of claim 8, wherein the matrixrepresents any of a correlation of code sequences for the userwaveforms, a cross-correlation of the user waveforms based on time-lagsand complex amplitudes, and estimates of user transmitted symbolsembedded in the user waveforms.
 10. A communications device fordetecting user transmitted symbols encoded in spread spectrum waveforms(hereinafter “user waveforms”) comprising a first process operatingunder a first operating system and executing a first set ofcommunication tasks for detecting user transmitted symbols encoded inthe user waveforms, a plurality of second processes each operating undera second operating system and executing a respective second set ofcommunication tasks for detecting user transmitted symbols encoded inthe user waveforms, where the first and second operation systems differ,a protocol translator coupled to the first and second processes andtranslating communications in between, the first process sending to eachsecond process via the protocol translator a set of executableinstructions for performing a respective portion of a common task. 11.The device of claim 10, wherein the first process sends to each of thesecond processes via the protocol translator instructions for generatinga respective portion of a matrix.
 12. The device of claim 11, whereinthe first process sends to each of the second processes via the protocoltranslator instructions for generation the portion of a matrixrepresenting of any of a correlation of code sequences for the userwaveforms, a portion of a cross-correlation of the user waveforms basedon time-lags and complex amplitudes, and estimates of user transmittedsymbols embedded in the user waveforms.
 13. The device of claim 11,wherein the first process sends via the protocol translator to eachsecond process information for configuration thereof.
 14. The device ofclaim 13, wherein the each of the second processes routes its respectiveportion of a matrix to one or more memories and devices based on theinformation from the first process.
 15. The device of claim 13, whereinthe first process monitors an operational status of each of the secondprocesses and generates the information for configuration thereof basedtheron.
 16. The device of claim 13, wherein the first process monitorsan operational status of each of the second processes and generates theset of executable instructions thereof based theron.
 17. Acommunications device for detecting user transmitted symbols encoded incode spread spectrum waveforms (hereinafter “user waveforms”) comprisinga first process operating under a first operating system and executing afirst set of communication tasks for detecting user transmitted symbolsencoded in the user waveforms, a second process operating under a secondoperating system, and executing a second set of communication tasks fordetecting user transmitted symbols encoded in the user waveforms, wherethe first and second operation systems differ, a protocol translatorcoupled to the first and second processes and translating communicationsin between, the first process sending instructions to the protocoltranslator for determining how it tranlates communication between thefirst and second processes.
 18. The device of claim 17, wherein thefirst process sends to each of the second processes via the protocoltranslator instructions for generating a respective portion of a matrix.19. The device of claim 18, wherein the first process sends to each ofthe second processes via the protocol translator instructions forgeneration the portion of a matrix representing of any of a correlationof code sequences for the user waveforms, a portion of across-correlation of the user waveforms based on time-lags and complexamplitudes, and estimates of user transmitted symbols embedded in theuser waveforms.